AIR GAP ARCHITECTURE FOR HIGH SPEED I/O SUBSTRATE TRACES
Microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. A conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. A first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.
1 . An integrated circuit package structure, comprising:
a first substrate comprising a first metal structure on a surface of the first substrate;
a second substrate comprising a second metal structure on a surface of the second substrate, wherein the first and second metal structures are in direct physical contact at a bonding interface therebetween;
a conductive trace on the surface of the first substrate adjacent to the bonding interface and over a recessed surface of the first substrate; and
a first air gap between the conductive trace and the bonding interface and a second air gap between the conductive trace and the recessed surface of the first substrate.
2 . The integrated circuit package structure of claim 1 , wherein the first and second substrates comprise glass.
3 . The integrated circuit package structure of claim 1 , wherein a portion of the first air gap is between the first substrate and the second substrate.
4 . The integrated circuit package structure of claim 1 , wherein the first metal structure and the conductive trace comprise the same material.
5 . The integrated circuit package structure of claim 4 , wherein a third air gap is adjacent the second air gap.
6 . The integrated circuit package structure of claim 5 , wherein a pylon is between the second air gap and the third air gap.
7 . The integrated circuit package structure of claim 6 , wherein a portion of the conductive trace on the pylon comprises one of a narrowed width or a rectangular extension.
8 . The integrated circuit package structure of claim 1 , wherein the second substrate comprises a third metal structure on a side opposite the second metal structure, wherein the third metal structure is in direct physical contact with a fourth metal structure on a surface of a third substrate, and wherein a third air gap is between the fourth metal structure and a conductive trace on the surface of the third substrate.
9 . The integrated circuit package structure of claim 8 , wherein the conductive trace comprises a high speed trace.
10 . The integrated circuit package structure of claim 1 , wherein the first metal structure and the conductive trace comprise substantially the same thickness.
11 . A an integrated circuit (IC) package structure, comprising:
a first substrate comprising a first plane structure on a surface of the first substrate;
a second substrate comprising a second plane structure on a surface of the second substrate, wherein the first and second plane structures are in direct physical contact with each other;
a conductive trace on the surface of the first substrate adjacent to the first plane structure;
an air gap between the conductive trace and a bond interface between the first and second plane structures;
an integrated circuit die coupled to at least one of the first substrate or the second substrate; and
a power supply coupled to IC package to provide power to the integrated circuit die.
12 . The package structure of claim 11 , wherein the first and second plane structures comprise a dielectric material or a conductive material.
13 . The package structure of claim 12 , wherein the conductive material comprises copper or a copper alloy.
14 . The package structure of claim 12 , wherein the dielectric material comprises one or more of silicon, nitrogen, or oxygen.
15 . The package structure of claim 11 , wherein the first and second plane structures comprise a combined height of between 1 micron and 100 microns.
16 . The package structure of claim 11 , wherein a height of the air gap is between 1 micron to 30 microns.
17 . The package structure of claim 11 wherein the conductive trace is substantially coplanar with the bond interface.
18 . A method of forming a package structure, comprising:
forming an opening in a first substrate, the opening defining a recessed surface of the first substrate;
forming a dielectric material within the opening;
forming a first bond plane feature on peripheral regions of the first substrate;
forming a conductive trace on the first substrate adjacent to the first bond plane feature;
removing the dielectric material to form an air gap between the conductive trace and the recessed surface; and
bonding a second bond plane feature of a second substrate to the first bond plane feature of the first substrate.
19 . The method of claim 18 , wherein forming the first bond plane feature comprises forming the first bond plane feature coplanar with the conductive trace.
20 . The method of claim 19 , wherein forming the first bond plane feature comprises forming one of a metal plane structure or a dielectric plane structure.