Highly scalable quantum control
A system comprising a quantum control data exchange circuit that enables a large, variable number of pulse generation circuits to exchange data within the coherence time of a plurality of quantum elements to enable feedback-based quantum control of a large, variable number of quantum elements.
1 . A system comprising:
a plurality of quantum control pulse generation circuits;
a memory; and
an interface circuit operable to:
receive a message comprising an opcode,
in response to the opcode being a sync opcode, generate a sync indication according to the interface circuit,
in response to the opcode being a write opcode, extract data from the message and write the data to the memory, and
in response to the opcode being a read opcode, read data from the memory and transmit the read data to a designated quantum control pulse generation circuit of the plurality of quantum control pulse generation circuits.
2 . The system of claim 1 , wherein a destination for the sync indication is determined according to a sync map in the memory.
3 . The system of claim 1 , wherein:
the memory comprises a sync map,
for each of a plurality of time intervals, the sync map designates which of the plurality of quantum control pulse generation circuits are to be synchronized during that time interval,
a first two or more of the plurality of quantum control pulse generation circuits are synchronized during a first of the plurality of time intervals, and
a second two or more of the plurality of quantum control pulse generation circuits are synchronized during a second of the plurality of time intervals.
4 . The system of claim 1 , wherein the interface circuit is operable to:
in response to the opcode being a write opcode, detect whether the write opcode is a first-type write opcode or a second-type write opcode;
if the opcode is a first-type write opcode, write the data to a first register of the memory; and
if the opcode is a second-type write opcode, write the data to a second register of the memory.
5 . The system of claim 1 , wherein:
the interface circuit is operable to, in response to the opcode being a read opcode, extract an index from the message; and
determine a location within the memory from which to perform the read of the read data based on the index.
6 . The system of claim 1 , wherein an index corresponds to which of the plurality of quantum control pulse generation circuits the read data originated.
7 . The system of claim 1 , wherein the interface circuit is operable to:
in response to the opcode being a read opcode, detect whether the read opcode is a first-type read opcode or a second-type read opcode;
if the read opcode is a first-type read opcode, read data from a first register of the memory; and
if the read opcode is a second-type read opcode, read data from a second register of the memory.
8 . The system of claim 1 , wherein:
a first quantum control pulse generation circuit comprises a first processor;
a second quantum control pulse generation circuit comprises a second processor;
the first quantum control pulse generation circuit is operable to:
receive a value generated by the second processor;
determine phase, frequency, timing and/or amplitude of a quantum control pulse according to the value generated by the second processor; and
generate the quantum control pulse.
9 . The system of claim 1 , wherein a first quantum control pulse generation circuit is operable to determine a phase, frequency, timing, and/or amplitude of a quantum control pulse.
10 . A method comprising:
in an interface circuit:
receiving a message comprising an opcode,
in response to the opcode being a sync opcode, generating a sync indication according to the interface circuit,
in response to the opcode being a write opcode, extracting data from the message and writing the data to a memory, and
in response to the opcode being a read opcode, reading data from the memory and transmitting the read data to a designated quantum control pulse generation circuit of a plurality of quantum control pulse generation circuits.
11 . The method of claim 10 , wherein the method comprises determining a destination for the sync indication according to a sync map in the memory.
12 . The method of claim 10 , wherein:
the memory comprises a sync map,
for each of a plurality of time intervals, the sync map designates which of the plurality of quantum control pulse generation circuits are to be synchronized during that time interval,
a first two or more of the plurality of quantum control pulse generation circuits are synchronized during a first of the plurality of time intervals, and
a second two or more of the plurality of quantum control pulse generation circuits are synchronized during a second of the plurality of time intervals.
13 . The method of claim 10 , wherein the method comprises:
in the interface circuit:
in response to the opcode being a write opcode, detecting whether the write opcode is a first-type write opcode or a second-type write opcode;
if the opcode is a first-type write opcode, writing the data to a first register of the memory; and
if the opcode is a second-type write opcode, writing the data to a second register of the memory.
14 . The method of claim 10 , wherein the method comprises:
in the interface circuit:
in response to the opcode being a read opcode, extracting an index from the message; and
determining a location within the memory from which to perform the read of the read data according to the index.
15 . The method of claim 10 , wherein an index corresponds to which of the plurality of quantum control pulse generation circuits the read data originated.
16 . The method of claim 10 , wherein the method comprises:
in the interface circuit:
in response to the opcode being a read opcode, detecting whether the read opcode is a first-type read opcode or a second-type read opcode;
if the read opcode is a first-type read opcode, reading data from a first register of the memory; and
if the read opcode is a second-type read opcode, reading data from a second register of the memory.
17 . The method of claim 10 , wherein:
a first quantum control pulse generation circuit comprises a first processor;
a second quantum control pulse generation circuit comprises a second processor;
the first quantum control pulse generation circuit is operable to:
receive a value generated by the second processor;
determine phase, frequency, timing and/or amplitude of a quantum control pulse according to the value generated by the second processor; and
generate the quantum control pulse.
18 . The method of claim 10 , wherein a first quantum control pulse generation circuit is operable to determine a phase, frequency, timing, and/or amplitude of a quantum control pulse.