Discrete three-dimensional processor
A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.
1. A discrete three-dimensional (3-D) processor, comprising:
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of an address decoder of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said address decoder; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
2. The 3-D processor according to claim 1 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
3. The 3-D processor according to claim 1 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
4. The 3-D processor according to claim 1 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
5. The 3-D processor according to claim 1 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.
6. A discrete three-dimensional (3-D) processor, comprising:
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a sense amplifier of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said sense amplifier; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
7. The 3-D processor according to claim 6 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
8. The 3-D processor according to claim 6 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
9. The 3-D processor according to claim 6 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
10. The 3-D processor according to claim 6 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.
11. A discrete three-dimensional (3-D) processor, comprising:
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a programming circuit of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said programming circuit; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
12. The 3-D processor according to claim 11 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
13. The 3-D processor according to claim 11 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
14. The 3-D processor according to claim 11 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
15. The 3-D processor according to claim 11 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.
16. A discrete three-dimensional (3-D) processor, comprising:
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a read-voltage generator of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said read-voltage generator; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
17. The 3-D processor according to claim 16 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
18. The 3-D processor according to claim 16 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
19. The 3-D processor according to claim 16 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
20. The 3-D processor according to claim 16 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.
21. A discrete three-dimensional (3-D) processor, comprising:
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a write-voltage generator of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said write-voltage generator; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
22. The 3-D processor according to claim 21 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
23. The 3-D processor according to claim 21 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
24. The 3-D processor according to claim 21 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
25. The 3-D processor according to claim 21 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.
26. A discrete three-dimensional (3-D) processor, comprising:
a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a data buffer of said 3D-M array disposed on said second semiconductor substrate;
wherein, said logic circuit processes data stored in said 3D-M array; said logic circuit is not a portion of a peripheral circuit of said 3D-M array; said first die does not comprise said portion of said data buffer; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate substrates.
27. The 3-D processor according to claim 26 , further comprising a plurality of storage-processing units (SPU's)
each of said SPU's comprising one logic circuit and one 3D-M array; or,
each of said SPU's comprising one logic circuit and more than one 3D-M arrays;
wherein, said logic circuit is said one logic circuit in a selected one of said plurality of SPU's; and, said 3D-M array is said one 3D-M array or another selected one of said more than one 3D-M arrays in said selected one of said plurality of SPU's.
28. The 3-D processor according to claim 26 , wherein:
said logic circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said logic circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.
29. The 3-D processor according to claim 26 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said logic circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a logic circuit; or,
each logic circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said logic circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).
30. The 3-D processor according to claim 26 , wherein:
said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or,
said 3D-M array is a horizontal 3D-M (3D-M H ) array; or,
said 3D-M array is a vertical 3D-M (3D-M V ) array; or,
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
at least a portion of the interconnect material used in said second die has a lower resistivity than at least another portion of the interconnect material used in said first die.