Memory system performing read operation with read voltage
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
1. A memory system comprising:
a nonvolatile semiconductor memory device including a memory cell, and
a control circuit configured to:
cause the nonvolatile semiconductor memory device to execute a first read operation to the memory cell with a first voltage,
cause, based on an error being detected on data read by the first read operation, the nonvolatile semiconductor memory device to execute a second read operation to the memory cell with a second voltage that is shifted to a first direction by certain voltage from the first voltage,
record data related to a value of the second voltage based on no error being detected on the data read by the second read operation,
cause, based on an error being detected on data read in the second read operation, the nonvolatile semiconductor memory device to execute a third read operation with a third voltage that is shifted to a second direction by certain voltage from the first voltage, the second direction being opposite direction to the first direction, and
record data related to a value of the third voltage based on no error being detected on data read in the third read operation.
2. The memory system of claim 1 , wherein:
the second voltage is higher than the first voltage, and
the third voltage is lower than the first voltage.
3. The memory system of claim 1 , wherein the second read operation is a retry read operation to the memory cell, the retry read operation is executed after the error is detected.
4. The memory system of claim 1 , wherein the second voltage is higher or lower than the first voltage.
5. The memory system of claim 1 , wherein a time of the first read operation is different from a time of the second read operation.
6. The memory system of claim 1 , wherein a fourth voltage supplied to an unselected word line adjacent to a selected word line in the second read operation is higher than a fifth voltage supplied to the unselected word line in the first read operation.
7. The memory system of claim 1 , wherein the control circuit is further configured to record the data related to the value of the second voltage in a case where the second voltage is set based on a standing time of the nonvolatile semiconductor memory device.
8. The memory system of claim 1 , wherein the control circuit is further configured to record the data related to the value of the second voltage in a case where the second voltage is set based on at least one of a write count, an erase count, and a read count.
9. A method of memory system comprising a nonvolatile semiconductor memory device including a memory cell, the method comprising:
causing the nonvolatile semiconductor memory device to execute a first read operation to the memory cell with a first voltage, and
causing, based on an error being detected on data read by the first read operation, the nonvolatile semiconductor memory device to execute a second read operation to the memory cell with a second voltage that is shifted to a first direction by certain voltage from the first voltage,
recording data related to a value of the second voltage based on an error being detected on data read by the second read operation,
causing, based on an error being detected on data read in the second read operation, the nonvolatile semiconductor memory device to execute a third read operation with a third voltage that is shifted to a second direction by certain voltage from the first voltage, the second direction being opposite direction to the first direction, and
recording data related to a value of the third voltage based on no error being detected on data read in the third read operation.
10. The method of claim 9 , wherein:
the second voltage is higher than the first voltage, and the third voltage is lower than the first voltage.
11. The method of claim 9 , wherein the second read operation is a retry read operation to the memory cell, the retry read operation is executed after the error is detected.
12. The method of claim 9 , wherein the second voltage is higher or lower than the first voltage.
13. The method of claim 9 , wherein a time of the first read operation is different from a time of the second read operation.
14. The method of claim 9 , wherein a fourth voltage supplied to an unselected word line adjacent to a selected word line in the second read operation is higher than a fifth voltage supplied to the unselected word line in the first read operation.
15. The method of claim 9 , further comprising:
recording the data related to the value of the second voltage in a case where the second voltage is set based on a standing time of the nonvolatile semiconductor memory device.
16. The method of claim 9 , further comprising:
recording the data related to the value of the second voltage in a case where the second voltage is set based on at least one of a write count, an erase count, and a read count.
17. The memory system of claim 1 , wherein the nonvolatile semiconductor memory device includes a NAND type flash memory.
18. The memory system of claim 1 , wherein:
the second voltage is lower than the first voltage, and
the third voltage is higher than the first voltage.
19. The method of claim 9 , wherein the nonvolatile semiconductor memory device includes a NAND type flash memory.
20. The method of claim 9 , wherein:
the second voltage is lower than the first voltage, and
the third voltage is higher than the first voltage.