Semiconductor device
A semiconductor device may include a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate including a memory cell region, a peripheral circuit region, and a boundary region between the memory cell region and the peripheral circuit region, first active patterns in the memory cell region, each of the first active patterns extending in a third direction oblique to the first direction, and a silicon dam structure in the boundary region. The silicon dam structure may include a silicon dam pattern including trench lines extending in the oblique direction and a dam isolation pattern in the trench lines.
1 . A semiconductor device, comprising:
a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate including a memory cell region, a peripheral circuit region, and a boundary region between the memory cell region and the peripheral circuit region, the memory cell region when viewed in a plan view having a first straight horizontal edge portion extending in the second direction and a second straight horizontal edge portion extending in the first direction;
first active patterns in the memory cell region, each of the first active patterns extending in a third direction oblique to the first direction; and
a first silicon dam structure in the boundary region adjacent to the first straight horizontal edge portion of the memory cell region in the first direction, and the first silicon dam structure extends in the second direction,
a second silicon dam structure in the boundary region adjacent to the second straight horizontal edge portion of the memory cell region in the second direction, and the second silicon dam structure extends in the first direction,
wherein the first silicon dam structure includes a first silicon dam pattern including first trench lines and a first dam isolation pattern in the first trench lines,
wherein the second silicon dam structure includes a second silicon dam pattern including second trench lines and a second dam isolation pattern in the second trench lines,
wherein, when viewed in a plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from the first active patterns,
wherein, when viewed in the plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from edges of the memory cell region,
wherein, when viewed in the plan view, the first trench lines partially extend through the first silicon dam pattern in the third direction, and
wherein, when viewed in the plan view, the second trench lines completely extend through the second silicon dam pattern in the third direction.
2 . The semiconductor device of claim 1 , wherein each of the first active patterns has a first line width, and an inner width of the first trench lines is the same as the first line width.
3 . The semiconductor device of claim 1 , further comprising:
a first isolation trench disposed between the first silicon dam structure and the memory cell region in the first direction; and
a second isolation trench disposed between the second silicon dam structure and the memory cell region in the second direction,
wherein the first isolation trench and the second isolation trench include an isolation pattern therein, and a first width of the first isolation trench in the first direction is greater than a second width of the second isolation trench in the second direction.
4 . The semiconductor device of claim 3 , further comprising:
a third isolation trench disposed between the first silicon dam structure and the peripheral circuit region; and
a fourth isolation trench disposed between the second silicon dam structure and the peripheral circuit region,
wherein the third isolation trench and the fourth isolation trench include an isolation pattern therein, and a third width of the third isolation trench in the first direction is less than a fourth width of the fourth isolation trench in the second direction.
5 . The semiconductor device of claim 3 , wherein the first silicon dam structure includes a plurality of first silicon dam patterns,
wherein the first silicon dam patterns are arranged in the second direction to be spaced apart from each other in the second direction, and
wherein each of the first silicon dam patterns includes first trench lines extending in the third direction.
6 . The semiconductor device of claim 1 ,
wherein a third distance from the memory cell region to a first side of the second silicon dam structure facing the memory cell region is less than a fourth distance from the peripheral circuit region to a second side of the second silicon dam structure facing the peripheral circuit region.
7 . The semiconductor device of claim 3 , wherein an end of the first silicon dam structure and an end of the second silicon dam structure are spaced apart from each other.
8 . The semiconductor device of claim 3 , wherein an end of the first silicon dam structure and an end of the second silicon dam structure are connected to each other, and the first silicon dam structure and the second silicon dam structure form a frame shape surrounding the memory cell region.
9 . The semiconductor device of claim 3 ,
wherein the first dam isolation pattern and the second dam isolation pattern include only an inner wall oxide layer pattern, and the isolation pattern includes the inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern.
10 . The semiconductor device of claim 9 , wherein the filling insulation pattern includes Tonen silazane (TOSZ).
11 . A semiconductor device, comprising:
a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate including a memory cell region, a peripheral circuit region, and a boundary region between the memory cell region and the peripheral circuit region, the memory cell region when viewed in a plan view having a first straight horizontal edge portion extending in the second direction and a second straight horizontal edge portion extending in the first direction;
first active patterns in the memory cell region, each of the first active patterns extending in a third direction oblique to the first direction;
a first silicon dam structure extending in the second direction and positioned in the boundary region adjacent to the first straight horizontal edge portion of the memory cell region in the first direction, the first silicon dam structure including a first silicon dam pattern including first trench lines extending in the third direction and a first dam isolation pattern in the first trench lines;
a second silicon dam structure extending in the first direction and positioned in the boundary region adjacent to the second straight horizontal edge portion of the memory cell region in the second direction, the second silicon dam structure including a second silicon dam pattern including second trench lines extending in the third direction and a second dam isolation pattern in the second trench lines; and
an isolation pattern positioned in the boundary region in addition to the first and second silicon dam structures,
wherein, when viewed in a plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from the first active patterns,
wherein, when viewed in the plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from edges of the memory cell region,
wherein, when viewed in the plan view, the first trench lines partially extend through the first silicon dam pattern in the third direction, and
wherein, when viewed in the plan view, the second trench lines completely extend through the second silicon dam pattern in the third direction.
12 . The semiconductor device of claim 11 , further comprising:
a first isolation trench disposed between the first silicon dam structure and the memory cell region in the first direction; and
a second isolation trench disposed between the second silicon dam structure and the memory cell region in the second direction,
wherein the first isolation trench and the second isolation trench include an isolation pattern therein, and a first width of the first isolation trench in the first direction is greater than a second width of the second isolation trench in the second direction.
13 . The semiconductor device of claim 11 , wherein the first silicon dam pattern is one of a plurality of first silicon dam patterns that are included in the first silicon dam structure,
wherein the first silicon dam patterns are arranged in the second direction to be spaced apart from each other in the second direction, and
wherein the first trench lines are formed in at least a portion of the first silicon dam patterns.
14 . The semiconductor device of claim 11 , further comprising:
a third isolation trench disposed between the first silicon dam structure and the peripheral circuit region; and
a fourth isolation trench disposed between the second silicon dam structure and the peripheral circuit region,
wherein the third isolation trench and the fourth isolation trench include an isolation pattern therein, and a third width of the third isolation trench in the first direction is less than a fourth width of the fourth isolation trench in the second direction.
15 . The semiconductor device of claim 11 , wherein the first and second dam isolation patterns include only an inner wall oxide layer pattern, and the isolation pattern includes the inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern.
16 . The semiconductor device of claim 15 , wherein the filling insulation pattern includes Tonen silazane (TOSZ).
17 . A semiconductor device, comprising:
a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate including a memory cell region, a peripheral circuit region, and a boundary region between the memory cell region and the peripheral circuit region, the memory cell region when viewed in a plan view having a first straight horizontal edge portion extending in the second direction and a second straight horizontal edge portion extending in the first direction;
first active patterns in the memory cell region, each of the first active patterns extending in a third direction oblique to the first direction;
a first silicon dam structure extending in the second direction and positioned in the boundary region adjacent to the first straight horizontal edge portion of the memory cell region in the first direction, the first silicon dam structure including a first silicon dam pattern including first trench lines extending in the third direction and a first dam isolation pattern in the first trench lines;
a second silicon dam structure extending in the first direction and positioned in the boundary region adjacent to the second straight horizontal edge portion of the memory cell region in the second direction, the second silicon dam structure including a second silicon dam pattern including second trench lines extending in the third direction and a second dam isolation pattern in the second trench lines;
a gate structure in the memory cell region, the gate structure extending in the first direction;
bit line structures in the memory cell region, the bit line structures extending in the second direction, and the bit line structures including a polysilicon pattern;
a contact plug structure disposed between the bit line structures in the memory cell region; and
a capacitor on the contact plug structure, the capacitor being electrically connected to the contact plug structure,
wherein, when viewed in a plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from the first active patterns,
wherein, when viewed in the plan view, the first silicon dam pattern and the second silicon dam pattern are spaced apart from edges of the memory cell region,
wherein, when viewed in the plan view, the first trench lines partially extend through the first silicon dam pattern in the third direction, and
wherein, when viewed in the plan view, the second trench lines completely extend through the second silicon dam pattern in the third direction.
18 . The semiconductor device of claim 17 , wherein each of the first active patterns has a first line width, and an inner width of each of the first trench lines and the second trench lines is the same as the first line width.