Memory circuit, system and method for rapid retrieval of data sets
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
1. A memory array comprising a plurality of bit lines, a plurality of word lines, one or more source lines, a plurality of memory strings and a plurality of sense amplifiers, wherein (i) each memory string comprises a plurality of memory cells sharing an associated one of the bit lines, an associated one of the source lines, and an associated group of word lines, and (ii) each memory cell of each memory string, when selected during a read operation, provides a data signal representing content that is stored in the memory cell on the associated bit line of the memory cell, after biasing the associated bit line, the associate source line and the associated word line according to a predetermined manner; and wherein (i) the memory cells of the memory array are further grouped into one of more data groups of memory cells and one or more reference groups of memory cells; (ii) each memory cell in each data group is associated with a corresponding one of the memory cells in a corresponding one of the reference groups; and (iii) each memory cell in each data group and its corresponding memory cell in the corresponding reference group together are associated with a designated one of the plurality of sense amplifiers, such that, when that memory cell of that data group is selected during the read operation, the data signal of that memory cell and the data signal of its corresponding memory cell in the corresponding reference group are provided on their respective associated bit lines to the designated sense amplifier, which provides an output value representative of the content of that selected memory cell.
2. The memory array of claim 1 , wherein each memory string comprises a NOR memory string.
3. The memory array of claim 1 , wherein each data group and its corresponding reference group are each formed out of a predetermined number of the memory strings.
4. The memory array of claim 3 , wherein each data group comprises a single memory string.
5. The memory array of claim 3 , wherein the predetermined number of memory strings of the data group and the predetermined number of its corresponding reference group each form a 2-dimensional array of the memory strings.
6. The memory array of claim 5 , wherein the 2-dimensional array comprises M rows and N columns, wherein M and N are both greater than 1.
7. The memory array of claim 5 , wherein the predetermined number of memory strings of the data group are organized as M rows or N columns.
8. The memory array of claim 5 , wherein the memory cells of the data group are associated with the same word line.
9. The memory array of claim 5 , wherein the memory cells of the data group and their corresponding memory cells of their corresponding reference group are associated with the same word line.
10. The memory array of claim 3 , wherein the memory cells of the data group are selected simultaneously, such that their designated sense amplifiers provide their output data substantially simultaneously.
11. The memory array of claim 3 , wherein the predetermined number of memory strings of data group and the predetermined number of its corresponding reference group each form a 2-dimensional array of the memory strings.
12. The memory array of claim 1 , wherein the memory array comprises a plurality of blocks and wherein each data group and its corresponding reference group are placed into physically adjacent blocks.
13. The memory array of claim 12 , wherein the blocks are placed in the form of one or more sets of quadrants.
14. The memory array of claim 13 , wherein each set of quadrants includes four quadrants organized as two sets of mirror-imaged adjacent blocks.
15. The memory array of claim 12 , wherein the designated sense amplifiers associated with the data group and its corresponding reference group are placed adjacent to the physically adjacent blocks.
16. The memory array of claim 1 , wherein each sense amplifier uses the data signals received to eliminate a leakage current.
17. The memory array of claim 16 , wherein the memory cells in each data group have a lesser retention time than their corresponding memory cells in the corresponding reference group.
18. The memory array of claim 1 , wherein the memory cells of the memory array comprise one or more redundant reference groups, each redundant reference group being configurable to replace any one of the reference groups.
19. The memory array of claim 1 , wherein the memory cells of two or more of the data groups are associated with the same memory cells of the same reference group.
20. The memory array of claim 1 , wherein each data group and its corresponding reference group are placed such that each designated sense amplifier associated with the data group and its corresponding reference group receives its data signals at substantially the same time.
21. The memory array of claim 1 , wherein each sense amplifier comprises a differential sense amplifier.