IP Library › Granted Patent US 12,353,762
Granted Patent B2
US 12,353,762 · App. 17/980,546 · Granted Jul 8, 2025

Signal development caching in a memory device

Inventors: Dmitri A. Yudanov (Rancho Cordova, CA); Shanky Kumar Jain (Folsom, CA)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0673G06F9/546G06F12/0246G06F12/0802G06F12/0873G06F12/0875G06F12/0893G06F12/1045G11C7/08G11C7/1012G11C7/1063G11C7/109G11C8/08G11C11/221G11C11/2257G11C11/2259G11C11/2273G11C11/2275G11C11/2297G11C11/406G11C11/40603G11C11/4074G11C11/4085G11C11/4091G11C11/4096G06F2212/60G06F2212/608G06F2212/72G06F2212/7201
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Quick Facts
Patent No.
US 12,353,762
App. No.
17/980,546
Granted
Jul 8, 2025
Kind
B2
Abstract

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

Claims (86)

1. A method, comprising:

coupling a set of access lines of a memory array with a signal development cache, each of the set of access lines corresponding to a respective one of a set of memory cells of the memory array, wherein coupling the set of access lines with the signal development cache comprises:

coupling, during a first time interval, a first access line of the set of access lines with a first cache element of a plurality of cache elements of the signal development cache; and

coupling, during a second time interval that at least partially overlaps the first time interval, a second access line of the set of access lines with a second cache element of the plurality of cache elements;

storing, at each of the plurality of cache elements of the signal development cache and based at least in part on coupling the set of access lines with the signal development cache, a cache signal state corresponding to a logic state stored by a respective one of the set of memory cells;

coupling the plurality of cache elements of the signal development cache with a sense amplifier array based at least in part on the storing; and

sensing, at each of a plurality of sense amplifiers of the sense amplifier array, a respective logic signal based at least in part on a respective signal state stored and the coupling of the plurality of cache elements with the sense amplifier array.

2. The method of claim 1 , wherein coupling the signal development cache with the sense amplifier array comprises:

coupling, during a third time interval, the first cache element of the plurality of cache elements with a first sense amplifier of the sense amplifier array; and

coupling, during a fourth time interval that follows the third time interval, the second cache element of the plurality of cache elements with the first sense amplifier of the sense amplifier array.

3. The method of claim 1 , wherein coupling the signal development cache with the sense amplifier array comprises:

coupling, during a third time interval, the first cache element of the plurality of cache elements with a first sense amplifier of the sense amplifier array; and

coupling, during a fourth time interval that at least partially overlaps the third time interval, the second cache element of the plurality of cache elements with a second sense amplifier of the sense amplifier array.

4. The method of claim 1 , further comprising:

receiving, at a memory device, a read command from a requesting device, wherein coupling the set of access lines of the memory array with the signal development cache is based at least in part on the read command.

5. The method of claim 1 , further comprising:

receiving, at a memory device, a read command from a requesting device after storing the respective cache signal state at each of the plurality of cache elements of the signal development cache, wherein coupling the signal development cache with the sense amplifier array is based at least in part on the read command.

6. The method of claim 1 , wherein the memory array comprises a plurality of domains each associated with a respective subset of a plurality of word lines, the method further comprising:

activating a word line of a first domain of the plurality of domains to couple a first subset of the set of memory cells with a first subset of the set of access lines; and

activating a word line of a second domain of the plurality of domains to couple a second subset of the set of memory cells with a second subset of the set of access lines.

7. The method of claim 1 , wherein:

each of the set of memory cells comprises a ferroelectric capacitor; and

each of the plurality of cache elements comprises a linear capacitor.

8. A method, comprising:

activating a word line of a first domain, of a plurality of domains each associated with a respective subset of a plurality of word lines, to couple a first subset of a set of memory cells of a memory array with a first subset of a set of access lines of the memory array, wherein each of the plurality of domains is associated with one or more of a plurality of plate nodes that are each operable to be biased independent of other plate nodes of the plurality of plate nodes;

activating a word line of a second domain of the plurality of domains to couple a second subset of the set of memory cells with a second subset of the set of access lines;

biasing a plate node of the first domain;

biasing a plate node of the second domain;

coupling the set of access lines with a signal development cache, each of the set of access lines corresponding to a respective one of the set of memory cells;

storing, at each of a plurality of cache elements of the signal development cache and based at least in part on coupling the set of access lines with the signal development cache, a cache signal state corresponding to a logic state stored by a respective one of the set of memory cells, wherein storing the cache signal states corresponding to the logic states stored by the first subset of the set of memory cells is based at least in part on biasing the plate node of the first domain, and wherein storing the cache signal states corresponding to the logic states stored by the second subset of the set of memory cells is based at least in part on biasing the plate node of the second domain;

coupling the plurality of cache elements of the signal development cache with a sense amplifier array based at least in part on the storing; and

sensing, at each of a plurality of sense amplifiers of the sense amplifier array, a respective logic signal based at least in part on a respective signal state stored and the coupling of the plurality of cache elements with the sense amplifier array.

9. A memory device, comprising:

a memory array comprising a plurality of memory cells;

a signal development cache comprising a plurality of cache elements different than the plurality of memory cells;

a sense amplifier array comprising a plurality of sense amplifiers; and

one or more controllers operable to cause the memory device to:

couple a plurality of access lines of the memory array with the signal development cache, each of the plurality of access lines corresponding to a respective one of the plurality of memory cells, wherein, to couple the plurality of access lines of the memory array with the signal development cache, the one or more controllers are operable to cause the memory device to:

couple, during a first time interval, a first access line of the plurality of access lines with a first cache element of the plurality of cache elements; and

couple, during a second time interval that at least partially overlaps the first time interval, a second access line of the plurality of access lines with a second cache element of the plurality of cache elements;

store, at each of the plurality of cache elements and based at least in part on coupling the plurality of access lines with the signal development cache, a signal state corresponding to a logic state stored by a respective one of the plurality of memory cells;

couple the plurality of cache elements with the sense amplifier array based at least in part on the storing; and

sense at each of the plurality of sense amplifiers, a respective logic signal based at least in part on a respective signal state and coupling the plurality of cache elements with the sense amplifier array.

10. The memory device of claim 9 , wherein, to couple the signal development cache with the sense amplifier array, the one or more controllers are operable to cause the memory device to:

couple, during a third time interval, the first cache element of the plurality of cache elements with a first sense amplifier of the sense amplifier array; and

couple, during a fourth time interval that follows the third time interval, the second cache element of the plurality of cache elements with the first sense amplifier of the sense amplifier array.

11. The memory device of claim 9 , wherein, to couple the signal development cache with the sense amplifier array, the one or more controllers are operable to cause the memory device to:

couple, during a third time interval, the first cache element of the plurality of cache elements with a first sense amplifier of the sense amplifier array; and

couple, during a fourth time interval that at least partially overlaps the third time interval, the second cache element of the plurality of cache elements with a second sense amplifier of the sense amplifier array.

12. The memory device of claim 9 , wherein the one or more controllers are further operable to cause the memory device to:

receive a read command from a requesting device, wherein coupling the plurality of access lines of the memory array with the signal development cache is based at least in part on the read command.

13. The memory device of claim 9 , wherein the one or more controllers are further operable to cause the memory device to:

receive a read command from a requesting device after storing the respective cache signal state at each of the plurality of cache elements of the signal development cache, wherein coupling the signal development cache with the sense amplifier array is based at least in part on the read command.

14. The memory device of claim 9 , wherein the memory array comprises a plurality of domains each associated with a respective subset of a plurality of word lines, and the one or more controllers are further operable to cause the memory device to:

activate a word line of a first domain of the plurality of domains to couple a first subset of the plurality of memory cells with a first subset of the plurality of access lines; and

activate a word line of a second domain of the plurality of domains to couple a second subset of the plurality of memory cells with a second subset of the plurality of access lines.

15. The memory device of claim 9 , wherein:

each of the plurality of memory cells comprises a ferroelectric capacitor; and

each of the plurality of cache elements comprises a linear capacitor.

16. A memory device, comprising:

a memory array having a plurality of memory cells, each memory cell of the plurality of memory cells associated with one of a plurality of access lines of the memory array;

a signal development cache having a plurality of cache elements different than the plurality of memory cells of the memory array;

a sense amplifier array having a plurality of sense amplifiers, each sense amplifier of the plurality of sense amplifiers configured to output a logic state based at least in part on latching signaling from the signal development cache; and

selection circuitry operable to:

selectively couple the plurality of access lines of the memory array with the signal development cache, wherein, to couple the plurality of access lines of the memory array with the signal development cache, the selection circuitry is operable to:

couple, during a first time interval, a first access line of the plurality of access lines with a first cache element of the plurality of cache elements; and

couple, during a second time interval that at least partially overlaps the first time interval, a second access line of the plurality of access lines with a second cache element of the plurality of cache elements;

selectively couple the signal development cache with the plurality of sense amplifiers of the sense amplifier array;

selectively couple the plurality of access lines of the memory array with the plurality of sense amplifiers of the sense amplifier array;

or any combination thereof.

17. The memory device of claim 16 , wherein the selection circuitry is operable to support concurrent coupling of the plurality of access lines of the memory array, the signal development cache, and the plurality of sense amplifiers of the sense amplifier array.

18. The memory device of claim 16 , wherein the selection circuitry is operable to support concurrent coupling of one of the plurality of access lines of the memory array, one of the cache elements of the signal development cache, and one of the plurality of sense amplifiers of the sense amplifier array.

19. The memory device of claim 16 , wherein the selection circuitry is reconfigurable to support a change between policies for writing back information to the memory array.

20. A memory device, comprising:

a memory array comprising a plurality of memory cells and a plurality of domains, each of the plurality of domains associated with a respective subset of a plurality of word lines and associated with one or more of a plurality of plate nodes that are each operable to be biased independent of other plate nodes of the plurality of plate nodes;

a signal development cache comprising a plurality of cache elements different than the plurality of memory cells;

a sense amplifier array comprising a plurality of sense amplifiers; and

one or more controllers operable to cause the memory device to:

activate a word line of a first domain of the plurality of domains to couple a first subset of the plurality of memory cells with a first subset of a plurality of access lines of the memory array;

activate a word line of a second domain of the plurality of domains to couple a second subset of the plurality of memory cells with a second subset of the plurality of access lines;

bias a plate node of the first domain;

bias a plate node of the second domain;

couple the plurality of access lines with the signal development cache, each of the plurality of access lines corresponding to a respective one of the plurality of memory cells;

store, at each of the plurality of cache elements and based at least in part on coupling the plurality of access lines with the signal development cache, a signal state corresponding to a logic state stored by a respective one of the plurality of memory cells, wherein storing the cache signal states corresponding to the logic states stored by the first subset of the plurality of memory cells is based at least in part on biasing the plate node of the first domain, and wherein storing the cache signal states corresponding to the logic states stored by the second subset of the plurality of memory cells is based at least in part on biasing the plate node of the second domain;

couple the plurality of cache elements with the sense amplifier array based at least in part on the storing; and

sense at each of the plurality of sense amplifiers, a respective logic signal based at least in part on a respective signal state and coupling the plurality of cache elements with the sense amplifier array.

Continuity (3)
Division 17414296
Provisional Application 62783388 · Dec 21, 2018
Related Publication 20230066051A1 · Mar 2, 2023
References Cited (209)
US 4493026A · Olnowich · 1985 [cited by applicant]
US 5226009A · Arimoto · 1993 [cited by applicant]
US 5341501A · Keeley et al. · 1994 [cited by applicant]
US 5377154A · Takasugi · 1994 [cited by applicant]
US 5596521A · Tanaka et al. · 1997 [cited by applicant]
US 5787267A · Leung et al. · 1998 [cited by applicant]
US 5818787A · Miyamoto et al. · 1998 [cited by applicant]
US 5875452A · Katayama et al. · 1999 [cited by applicant]
US 5909407A · Yamamoto et al. · 1999 [cited by applicant]
US 6205076B1 · Wakayama et al. · 2001 [cited by applicant]
US 6320778B1 · Tanaka et al. · 2001 [cited by applicant]
US 7009880B1 · Liu · 2006 [cited by applicant]
US 7085190B2 · Worley et al. · 2006 [cited by applicant]
US 7216272B2 · Loh · 2007 [cited by applicant]
US 7286425B2 · Barth, Jr. · 2007 [cited by applicant]
US 8090999B2 · Roohparvar · 2012 [cited by applicant]
US 8873329B1 · Zheng et al. · 2014 [cited by applicant]
US 9313435B2 · Nitta et al. · 2016 [cited by applicant]
US 9443602B2 · Sakaue et al. · 2016 [cited by applicant]
US 9509317B2 · Masleid et al. · 2016 [cited by applicant]
US 9535844B1 · Cooney et al. · 2017 [cited by applicant]
US 9761312B1 · Kajigaya · 2017 [cited by applicant]
US 10153020B1 · Vimercati · 2018 [cited by applicant]
US 10153022B1 · Di Vincenzo · 2018 [cited by applicant]
US 10395710B1 · Abedifard et al. · 2019 [cited by applicant]
US 11372595B2 · Yudanov et al. · 2022 [cited by applicant]
US 20010026465A1 · Choi et al. · 2001 [cited by applicant]
US 20010050873A1 · Tanaka et al. · 2001 [cited by applicant]
US 20020067650A1 · Tanaka et al. · 2002 [cited by applicant]
US 20020154536A1 · Perner · 2002 [cited by applicant]
US 20020161967A1 · Kirihata et al. · 2002 [cited by applicant]
US 20020181307A1 · Fifield et al. · 2002 [cited by applicant]
US 20020186591A1 · Lee et al. · 2002 [cited by applicant]
US 20030021159A1 · Issa · 2003 [cited by applicant]
US 20030107923A1 · Roohparvar · 2003 [cited by applicant]
US 20040240288A1 · Takahashi · 2004 [cited by applicant]
US 20050030817A1 · Luk et al. · 2005 [cited by applicant]
US 20060056264A1 · Worley et al. · 2006 [cited by applicant]
US 20060087894A1 · Kim · 2006 [cited by applicant]
US 20060214086A1 · Fukushima · 2006 [cited by applicant]
US 20060221704A1 · Li et al. · 2006 [cited by applicant]
US 20070061507A1 · Iwanari et al. · 2007 [cited by applicant]
US 20070097768A1 · Barth · 2007 [cited by applicant]
US 20070168836A1 · Dempsey et al. · 2007 [cited by applicant]
US 20070250667A1 · Dement et al. · 2007 [cited by applicant]
US 20080037356A1 · Kajigaya · 2008 [cited by applicant]
US 20080080266A1 · Khellah et al. · 2008 [cited by applicant]
US 20080239811A1 · Tanaka · 2008 [cited by applicant]
US 20090129173A1 · Kajiyama et al. · 2009 [cited by applicant]
US 20090268537A1 · Kajigaya · 2009 [cited by applicant]
US 20100128515A1 · Fukushi · 2010 [cited by applicant]
US 20110044095A1 · Sato et al. · 2011 [cited by applicant]
US 20110119451A1 · Fuller et al. · 2011 [cited by applicant]
US 20110205776A1 · Murata · 2011 [cited by applicant]
US 20110208901A1 · Kim et al. · 2011 [cited by applicant]
US 20110246729A1 · Smith · 2011 [cited by applicant]
US 20110280086A1 · Choi et al. · 2011 [cited by applicant]
US 20120082174A1 · Chen et al. · 2012 [cited by applicant]
US 20120099390A1 · Cho · 2012 [cited by examiner]
US 20120127805A1 · Dreesen et al. · 2012 [cited by applicant]
US 20120151232A1 · Fish, III · 2012 [cited by applicant]
US 20120159076A1 · Tanpure et al. · 2012 [cited by applicant]
US 20120243304A1 · Hoya · 2012 [cited by applicant]
US 20120300566A1 · Mueller et al. · 2012 [cited by applicant]
US 20130145097A1 · Ingle et al. · 2013 [cited by applicant]
US 20130242684A1 · Takizawa · 2013 [cited by applicant]
US 20140177343A1 · Chan et al. · 2014 [cited by applicant]
US 20140181424A1 · Park · 2014 [cited by applicant]
US 20140325129A1 · Ahlquist · 2014 [cited by applicant]
US 20150130971A1 · Oike et al. · 2015 [cited by applicant]
US 20150229859A1 · Guidash et al. · 2015 [cited by applicant]
US 20160155481A1 · Park · 2016 [cited by applicant]
US 20160179685A1 · Byun · 2016 [cited by applicant]
US 20160239060A1 · Koob et al. · 2016 [cited by applicant]
US 20160283392A1 · Greenfield et al. · 2016 [cited by applicant]
US 20160336055A1 · Kato · 2016 [cited by applicant]
US 20160350230A1 · Murphy · 2016 [cited by applicant]
US 20170133096A1 · Yoo et al. · 2017 [cited by applicant]
US 20170153826A1 · Cho et al. · 2017 [cited by applicant]
US 20170263304A1 · Vimercati · 2017 [cited by applicant]
US 20170270051A1 · Chen et al. · 2017 [cited by applicant]
US 20170271019A1 · Park et al. · 2017 [cited by applicant]
US 20170277637A1 · Willcock et al. · 2017 [cited by applicant]
US 20170287541A1 · Vimercati · 2017 [cited by applicant]
US 20170309330A1 · Pyo · 2017 [cited by applicant]
US 20170315737A1 · Kajigaya · 2017 [cited by applicant]
US 20170337149A1 · Onuki et al. · 2017 [cited by applicant]
US 20170365358A1 · Ha · 2017 [cited by applicant]
US 20180081774A1 · Kawamura et al. · 2018 [cited by applicant]
US 20180096718A1 · Kim · 2018 [cited by examiner]
US 20180108393A1 · Vimercati · 2018 [cited by applicant]
US 20180130506A1 · Kang et al. · 2018 [cited by applicant]
US 20180150398A1 · Lu · 2018 [cited by applicant]
US 20180181344A1 · Tomishima et al. · 2018 [cited by applicant]
US 20180247687A1 · Vimercati · 2018 [cited by applicant]
US 20180301180A1 · Sano · 2018 [cited by applicant]
US 20180308538A1 · Vo et al. · 2018 [cited by applicant]
US 20180314635A1 · Alam · 2018 [cited by applicant]
US 20180349292A1 · Tal et al. · 2018 [cited by applicant]
US 20180358078A1 · Vimercati · 2018 [cited by applicant]
US 20190103145A1 · Tseng et al. · 2019 [cited by applicant]
US 20200042249A1 · Kang · 2020 [cited by examiner]
US 20200073812A1 · Willcock et al. · 2020 [cited by applicant]
US 20200135261A1 · Haraguchi et al. · 2020 [cited by applicant]
US 20210142845A1 · Murphy · 2021 [cited by applicant]
CN 1212430A · 1999 [cited by applicant]
CN 1480950A · 2004 [cited by applicant]
CN 1698132A · 2005 [cited by applicant]
CN 101063957A · 2007 [cited by applicant]
CN 101171641A · 2008 [cited by applicant]
CN 101379566A · 2009 [cited by applicant]
CN 101558390A · 2009 [cited by applicant]
CN 101743597A · 2010 [cited by applicant]
CN 102656639A · 2012 [cited by applicant]
CN 102800349A · 2012 [cited by applicant]
CN 103221929A · 2013 [cited by applicant]
CN 104078077A · 2014 [cited by applicant]
CN 105739914A · 2016 [cited by applicant]
CN 106463172A · 2017 [cited by applicant]
CN 106683692A · 2017 [cited by applicant]
CN 107240410A · 2017 [cited by applicant]
CN 107408405A · 2017 [cited by applicant]
CN 107430550A · 2017 [cited by applicant]
CN 107683505A · 2018 [cited by applicant]
CN 107924364A · 2018 [cited by applicant]
CN 108121671A · 2018 [cited by applicant]
CN 108701077A · 2018 [cited by applicant]
CN 108780656A · 2018 [cited by applicant]
CN 108885595A · 2018 [cited by applicant]
CN 108885891A · 2018 [cited by applicant]
EP 0662663A2 · 1995 [cited by applicant]
EP 0717412B1 · 2002 [cited by applicant]
JP 63197099A · 1988 [cited by applicant]
JP 01166850A · 1989 [cited by applicant]
JP 03015958A · 1991 [cited by applicant]
JP 05217374A · 1993 [cited by applicant]
JP 07211057A · 1995 [cited by applicant]
JP 07211061A · 1995 [cited by applicant]
JP 09180437A · 1997 [cited by applicant]
JP 11066850A · 1999 [cited by applicant]
JP 11073763A · 1999 [cited by applicant]
JP 11339466A · 1999 [cited by applicant]
JP 2000020396A · 2000 [cited by applicant]
JP 2001005725A · 2001 [cited by applicant]
JP 2001006379A · 2001 [cited by applicant]
JP 2001273193A · 2001 [cited by applicant]
JP 2002334580A · 2002 [cited by applicant]
JP 2003007049A · 2003 [cited by applicant]
JP 2004348916A · 2004 [cited by applicant]
JP 2006236304A · 2006 [cited by applicant]
JP 2007048286A · 2007 [cited by applicant]
JP 2007080325A · 2007 [cited by applicant]
JP 2012198972A · 2012 [cited by applicant]
JP 2012203938A · 2012 [cited by applicant]
JP 2013196717A · 2013 [cited by applicant]
JP 2017212022A · 2017 [cited by applicant]
JP 2018503903A · 2018 [cited by applicant]
JP 2018181394A · 2018 [cited by applicant]
KR 1020070066185A · 2007 [cited by applicant]
KR 1020100113389A · 2010 [cited by applicant]
TW 200426833A · 2004 [cited by applicant]
TW 201735038A · 2017 [cited by applicant]
TW 201805945A · 2018 [cited by applicant]
TW 201824280A · 2018 [cited by applicant]
TW I630621B · 2018 [cited by applicant]
WO 2017136203A1 · 2017 [cited by applicant]
WO 2017192759A1 · 2017 [cited by applicant]
WO 2018125385A1 · 2018 [cited by applicant]
WO 2018163252A1 · 2018 [cited by applicant]
Aboughazaleh, N. et al., “Near-memory Caching for Improved Energy Consumption”, Proceedings of the 2005 International Conference on Computer Design (ICCD'05), Oct. 2, 2005, pp. 105-110. [cited by applicant]
China National Intellectual Property Administration, “First Office Action,” issued in connection with Chinese Application No. 201980084160.X, dated Jan. 11, 2022 (13 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19898746.3 dated Sep. 9, 2022 (9 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19899500.3 dated Sep. 12, 2022 (9 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900061.3 dated Aug. 30, 2022 (9 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900287.4 dated Sep. 14, 2022 (11 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900288.2 dated Sep. 15, 2022 (10 pages). [cited by applicant]
European Patent Office, “Supplementary European search report and Search Opinion”, issued in connection with European Patent Application No. 19900916.8 dated Sep. 16, 2022 (10 pages). [cited by applicant]
Intellectual Property Office, “Office Action,” issued in connection with ROC (Taiwan) Patent Application No. 108144214, dated Oct. 26, 2020 (6 pages). [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/64597, mailed on Mar. 20, 2020, 9 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67829, mailed on Apr. 28, 2020, 13 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67832, mailed on Apr. 28, 2020, 9 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67834, mailed on Apr. 28, 2020, 10 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67838, mailed on Apr. 28, 2020, 10 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67840, mailed on Apr. 28, 2020, 7 pages. [cited by applicant]
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US19/67844, mailed on Apr. 8, 2020, 8 pages. [cited by applicant]
Japan Patent Office , “Notice of Rejection Ground,” issued in connection with Japanese Patent Application No. 2021-535559, dated Feb. 1, 2022 (10 pages). [cited by applicant]
Japan Patent Office, “Decision to Grant a Patent”, issued in connection with Japan Patent Application No. 2021-535529 dated Jun. 14, 2022 (5 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-533238 dated Sep. 6, 2022 (16 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-533432 dated Aug. 16, 2022 (29 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-535534 dated Jul. 5, 2022 (19 pages). [cited by applicant]
Japan Patent Office, “Notice of Rejection Ground”, issued in connection with Japan Patent Application No. 2021-535536 dated Jul. 5, 2022 (18 pages). [cited by applicant]
Japan Patent Office, “Office Action”, issued in connection with Japan Patent Application No. 2021-535540 dated Jun. 21, 2022 (17 pages). [cited by applicant]
Office Action received for Chinese Patent Application No. 201980084160.X, mailed on Jan. 11, 2022, 20 pages (8 pages of English Translation and 12 pages of Original Document). [cited by applicant]
Taiwan Intellectual Property Office, “Office Action,” issued in connection with ROC (Taiwan) Patent Application No. 108144214, dated Sep. 28, 2021 (18 pages with translation). [cited by applicant]
Cao, Z., et al., “Fast bipolar 1024-bit random access memory (RAM) for high performance storage system”, Computer research and development, Issue 01, Jan. 15, 1978, 7 pages. [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980082612.0 dated Oct. 9, 2023 (15 pages total; 7 pages Original & 8 pages machine translation). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980082657.8 dated Nov. 1, 2023 (29 pages total; 10 pages Original & 19 pages machine translation). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980084236.9 dated Sep. 4, 2023 (16 pages total; 8 pages Original & 8 pages machine translation). [cited by applicant]
Chinese Patent Office, “Office Action,” issued in connection with Chinese Patent Application No. 201980084464.6 dated Aug. 1, 2023 (32 pages) (12 pages of English Translation and 20 pages of Original Document). [cited by applicant]
Japan Patent Office, “Office Action,” issued in connection with Japan Patent Application No. 2022-168730 dated Sep. 5, 2023 (13 pages) (7 pages of English Translation and 6 pages of Original Document). [cited by applicant]
John Kirkwood, “Sybase SQL Server 11”, Hope, Oct. 31, 1998, pp. 169-270. [cited by applicant]
Xin, X., “Design and Application: CAM Based on FPGA”, Journal of National University of Defense Technology, vol. 23, No. 5, 2001, 5 pages. (English Abstract attached). [cited by applicant]
Zhou KE, Research on Storage Optimization Based on Solid State Drive's Characteristics, Huazhong University of Science & Technology, Feb. 2013, 116 pages. (English Abstract attached). [cited by applicant]
Chinese patent office, “CN Notice of Allowance, including Search Report,” issued in connection with China Patent Application No. 201980084464.6 dated Jul. 11, 2024 (8 pages total; 4 pages Original & 4 pages machine tran… [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084464.6 dated Feb. 23, 2024 (33 pages) (13 pages of English Translation and 20 pages of Original Document) . . … [cited by applicant]
Chinese patent office, “CN Notice of Allowance,” issued in connection with China Patent Application No. 201980084236.9 dated Feb. 4, 2024 (8 pages total; 4 pages Original & 4 pages translation). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084212.3 dated Oct. 31, 2024 (19 pages) (9 pages of English Translation and 10 pages of Original Document). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 201980084577.6 dated Oct. 31, 2024 (11 pages) (4 pages of English Translation and 7 pages of Original Document). [cited by applicant]
Chinese patent office, “China Office Action,” issued in connection with China Patent Application No. 202410511570.0 dated Feb. 27, 2025 (17 pages) (9 pages of English Translation and 8 pages of Original Document). [cited by applicant]
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US 12,640,191