Granted Patent B2

US 12,480,828 · App. 17/994,088 · Granted Nov 25, 2025

Inventors: Lawrence Natan (Chandler, AZ); Remrose Manuel (Cavite, PH); Adrian Arcedera (Chandler, AZ)

Assignee: Amkor Technology Singapore Holding Pte. Ltd.

G01L13/025G01L19/0038G01L19/147

Abstract

Claims (172)

1 . An electronic device, comprising:

a substrate structure comprising:

a first substrate comprising:

a first substrate inner side;

a first substrate outer side opposite to the first substrate inner side;

a first dielectric structure; and

a first conductive structure; and

a second substrate comprising:

a second substrate inner side;

a second substrate outer side;

a second dielectric structure comprising a first outer dielectric layer adjacent to the second substrate inner side;

a second conductive structure comprising:

second substrate inner terminals adjacent to the second substrate inner side and comprising a second substrate first inner terminal, wherein the second substrate first inner terminal is at a peripheral edge of the second substrate inner side and exposed from the first outer dielectric layer;

second substrate outer terminals adjacent to the second substrate outer side; second substrate traces adjacent to the second substrate inner side and coupled to the second substrate inner terminals; and

second substrate embedded vias connecting the second substrate inner terminals and the second substrate traces to the second substrate outer terminals;

a first opening extending from the second substrate inner side to the second substrate outer side;

a second opening extending from the second substrate inner side to the second substrate outer side and laterally spaced apart from the first opening;

an inner portion laterally extending between the first opening and the second opening; and

a peripheral portion surrounding the inner portion;

wherein:

the second substrate outer side is coupled to the first substrate inner side;

the inner portion of the second substrate is spaced apart from the first substrate inner side to define a passage between the second substrate and the first substrate; and

the passage is fluidly coupled with the first opening and the second opening;

a housing coupled to the second substrate and comprising:

a housing top;

housing walls;

a first port extending outward from the housing top; and

a second port extending outward from the housing top;

wherein:

the substrate structure, the housing top, and the housing walls define a first chamber and a second chamber isolated from the first chamber;

the first opening is within the second chamber;

the first port is fluidly coupled to the first chamber;

the housing walls are attached to the second substrate first inner terminal and the first outer dielectric layer, and

the second port is fluidly coupled to the second chamber; and

a first electronic component within the first chamber and comprising:

a top side; and

a lower side opposite to the top side and isolated from the top side;

wherein:

the top side is in fluid communication with the first chamber and the first port and is configured to receive a first stimulus; and

the lower side is in fluid communication with the second opening, the second chamber, and the second port and is configured to receive a second stimulus.

2 . The electronic device of claim 1 , wherein:

the second substrate outer side within the inner portion is devoid of the second conductive structure.

3 . The electronic device of claim 1 , further comprising:

an attachment material;

wherein:

the first dielectric structure comprises a second outer dielectric layer adjacent to the first substrate inner side;

the first conductive structure comprises:

first substrate inner terminals adjacent to the first substrate inner side and comprising a first substrate first inner terminal, wherein the first substrate first inner terminal is at a peripheral edge of the first substrate inner side and exposed from the second outer dielectric layer;

first substrate outer terminals adjacent to the first substrate outer side;

first substrate traces adjacent to the first substrate inner side and coupled to the first substrate inner terminals; and

first substrate embedded vias connecting the first substrate inner terminals and the first substrate traces to the first substrate outer terminals;

the second dielectric structure comprises a third outer dielectric layer adjacent to the second substrate outer side;

the second substrate outer terminals comprise a second substrate first outer terminal at a peripheral edge of the second substrate outer side and exposed from the third outer dielectric layer;

the second substrate first outer terminal is exposed from the third outer dielectric layer; and

the first substrate first inner terminal is directly attached to the second substrate first outer terminal with the attachment material.

4 . The electronic device of claim 1 , wherein:

the first electronic component is coupled to the second substrate inner side with the lower side aligned to the second opening.

5 . The electronic device of claim 1 , wherein:

the housing comprises a single-piece housing.

6 . The electronic device of claim 1 , wherein:

the passage is isolated from the first chamber.

7 . The electronic device of claim 1 , wherein:

the first electronic component comprises a sensor.

8 . The electronic device of claim 1 , further comprising:

an attachment material;

wherein:

the housing walls are directly attached to the second substrate first inner terminal and the first outer dielectric layer with the attachment material; and

the second substrate first inner terminal comprises a dummy structure.

9 . The electronic device of claim 1 , further comprising:

an attachment material;

substrate interconnects; and

a second electronic component coupled to the first electronic component and the substrate structure;

wherein:

the second conductive structure at the second substrate outer side is attached to the first conductive structure at the first substrate inner side with the substrate interconnects;

the second substrate outer side is attached to the first substrate inner side at a peripheral region with the attachment material; and

the attachment material provides an air-tight seal for the passage.

10 . The electronic device of claim 1 , wherein:

the first electronic component comprises a differential pressure sensor;

the top side of the first electronic component is configured to receive a first pressure stimulus; and

the lower side of the first electronic component is configured to receive a second pressure stimulus.

11 . An electronic device, comprising:

a substrate structure comprising:

substrate interconnects;

a first substrate comprising:

a first substrate inner side;

a first substrate outer side opposite to the first substrate inner side;

a first dielectric structure; and

a first conductive structure; and

a second substrate comprising:

a second substrate inner side;

a second substrate outer side;

a second dielectric structure comprising a first outer dielectric layer adjacent to the second substrate inner side;

a second conductive structure comprising:

second substrate inner terminals adjacent to the second substrate inner side;

second substrate outer terminals adjacent to the second substrate outer side;

second substrate traces adjacent to the second substrate inner side and coupled to the second substrate inner terminals;

second substrate embedded vias connecting the second substrate inner terminals to the second substrate outer terminals; and

a dummy structure at a peripheral edge of the second substrate inner side and exposed from the first outer dielectric layer;

a first opening extending from the second substrate inner side to the second substrate outer side;

a second opening extending from the second substrate inner side to the second substrate outer side and laterally spaced apart from the first opening;

an inner portion laterally extending between the first opening and the second opening and comprising a first thickness; and

a peripheral portion surrounding the inner portion and comprising a second thickness;

wherein:

the second conductive structure at the second substrate outer side is attached to the first conductive structure at the first substrate inner side with the substrate interconnects;

the substrate interconnects space the second substrate apart from the first substrate to define a first passage between the inner portion of the second substrate and the first substrate; and

the first passage is fluidly coupled with the first opening and the second opening;

a housing attached to the dummy structure and the first outer dielectric layer and comprising:

a first chamber;

a second chamber isolated from the first chamber;

a first port comprising a second passage coupled to the first chamber; and

a second port comprising a third passage coupled to the second chamber; and

a first electronic component within the first chamber and comprising:

a top side; and

a lower side opposite to the top side and isolated from the top side;

wherein:

the top side is configured to receive a first stimulus through the second passage and the first chamber; and

the lower side is configured to receive a second stimulus through the third passage, the second chamber, and the first passage.

12 . The electronic device of claim 11 , further comprising:

an attachment material;

wherein:

the housing is directly attached to the dummy structure and the first outer dielectric layer with the attachment material;

the substrate interconnects comprise sidewalls; and

the sidewalls are exposed within the first passage.

13 . The electronic device of claim 11 , wherein:

the second thickness is greater than the first thickness.

14 . The electronic device of claim 11 , wherein:

the housing comprises a stacked housing.

15 . A method of manufacturing an electronic device, comprising:

providing a substrate structure comprising:

substrate interconnects;

a first substrate comprising:

a first substrate inner side;

a first substrate outer side opposite to the first substrate inner side;

a first dielectric structure; and

a first conductive structure; and

a second substrate comprising:

a second substrate inner side;

a second substrate outer side;

a second dielectric structure comprising a first outer dielectric layer adjacent to the second substrate inner side;

a second conductive structure comprising:

second substrate inner terminals adjacent to the second substrate inner side;

second substrate outer terminals adjacent to the second substrate outer side;

second substrate traces adjacent to the second substrate inner side and coupled to the second substrate inner terminals;

second substrate embedded vias connecting the second substrate inner terminals to the second substrate outer terminals; and

a dummy structure at a peripheral edge of the second substrate inner side and exposed from the first outer dielectric layer;

a first opening extending from the second substrate inner side to the second substrate outer side;

a second opening extending from the second substrate inner side to the second substrate outer side and laterally spaced apart from the first opening;

an inner portion laterally extending between the first opening and the second opening; and

a peripheral portion surrounding the inner portion;

wherein:

the second conductive structure at the second substrate outer side is attached to the first conductive structure at the first substrate inner side with the substrate interconnects;

the substrate interconnects space the second substrate apart from the first substrate to define a first passage between the inner portion of the second substrate and the first substrate; and

the first passage is fluidly coupled with the first opening and the second opening;

providing a housing comprising:

a first chamber;

a second chamber isolated from the first chamber;

a first port comprising a second passage coupled to the first chamber; and

a second port comprising a third passage coupled to the second chamber;

providing a first electronic component comprising:

a top side; and

a lower side opposite to the top side;

coupling the first electronic component to one of the substrate structure or the housing within the first chamber; and

attaching the housing to the dummy structure and the first outer dielectric layer;

wherein:

the top side of the first electronic component is isolated from the lower side of the first electronic component;

the top side of the first electronic component is configured to receive a first stimulus within the first chamber; and

the lower side of the first electronic component is configured to receive a second stimulus through the third passage, the second chamber, and the first passage.

16 . The method of claim 15 , further comprising:

providing an attachment material;

wherein:

attaching the housing comprises directly attaching the housing to the dummy structure and the first outer dielectric layer with the attachment material; and

providing the substrate structure comprises exposing sidewall surfaces of the substrate interconnects with the first passage.

Assignments (4)

Continuity (1)

References Cited (10)