Trenched gate double diffused semiconductor device with channel impurity concentration adjustment region
In the present invention, in a FinFET having a channel forming region on a surface of a fin that is a semiconductor layer protruding on an upper surface of a substrate, a channel at a corner of the fin is prevented from becoming an ON state with a low voltage and a steep ON/OFF operation is made possible. As a means thereof, in a MOSFET that has a plurality of trenches, each of which have embedded therein a gate electrode, on an upper surface of an n-type epitaxial substrate provided with a drain region on a bottom surface and that has a channel region formed on a surface of a fin which is a protrusion part between the trenches adjacent to each other, a p-type body layer that constitutes a lateral surface of the fin, and a p + -type semiconductor region that constitutes a corner which is an end of the upper surface of the fin, are formed.
1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a plurality of trenches formed on an upper surface of the semiconductor substrate and arranged in a first direction;
a protruding portion protruding upward from a bottom surface of the trench between two of the trenches adjacent to each other in the first direction;
a first semiconductor region of a second conductivity type different from the first conductivity type, the first semiconductor region being formed in the protruding portion including a side surface of the protruding portion in the first direction;
a second semiconductor region of the second conductivity type that is formed at a corner portion which is an upper end of the side surface of the protruding portion and has impurity concentration twice or more than impurity concentration of the first semiconductor region;
a third semiconductor region of the first conductivity type connected to one end portion of the protruding portion in a second direction intersecting the first direction in plan view;
a fourth semiconductor region of the first conductivity type connected to another end portion of the protruding portion in the second direction; and
a gate electrode embedded inside each of a plurality of the trenches with a gate insulating film interposed therebetween, wherein
the gate electrode, the first semiconductor region, the third semiconductor region, and the fourth semiconductor region constitute a field effect transistor;
an end portion of the plurality of trenches on the second direction contacts to the third semiconductor region.
2. The semiconductor device according to claim 1 , further comprising:
a fifth semiconductor region of the second conductivity type formed on the upper surface of the semiconductor substrate; and
a sixth semiconductor region of the second conductivity type formed on the bottom surface of the trench and electrically connected to the first semiconductor region and the fifth semiconductor region, wherein
impurity concentration of the sixth semiconductor region is higher than the impurity concentration of the first semiconductor region, and impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the sixth semiconductor region.
3. The semiconductor device according to claim 1 , wherein
an end portion of the second semiconductor region in the first direction is located immediately above the third semiconductor region or immediately above the fourth semiconductor region.
4. The semiconductor device according to claim 1 , wherein
the second semiconductor region is formed at the corner portion of the protruding portion from one end portion to another end portion of the protruding portion in the first direction.
5. The semiconductor device according to claim 1 , wherein
a difference between a maximum value and a minimum value of threshold voltage of an upper surface of the protruding portion, threshold voltage of the corner portion, and threshold voltage of the side surface is 5 V or less.
6. The semiconductor device according to claim 1 , wherein
a depth of the second semiconductor region from an upper surface of the protruding portion is larger than film thickness of the gate insulating film covering the side surface of the protruding portion.
7. The semiconductor device according to claim 6 , wherein
the depth of the second semiconductor region is 200 nm or less.
8. The semiconductor device according to claim 1 , wherein
the semiconductor substrate contains silicon carbide.
9. The semiconductor device according to claim 1 , wherein
the third semiconductor region constitutes a source region, and
the fourth semiconductor region is electrically connected to a drain region formed on a bottom surface of the semiconductor substrate.
10. The semiconductor device according to claim 9 , further comprising:
a seventh semiconductor region of the first conductivity type formed adjacent to the fourth semiconductor region in the semiconductor substrate, wherein
the third semiconductor region, the trench, the fourth semiconductor region, and the seventh semiconductor region are arranged in order in the second direction,
impurity concentration of the seventh semiconductor region is lower than impurity concentration of the fourth semiconductor region,
the fourth semiconductor region is electrically connected to the drain region via the seventh semiconductor region, and
the second semiconductor region is formed from an upper surface of the protruding portion to immediately above the seventh semiconductor region.
11. The semiconductor device according to claim 1 , wherein
impurity concentration of the second semiconductor region gradually decreases from an upper surface of the protruding portion toward a lower surface of the second semiconductor region.
12. The semiconductor device according to claim 1 , wherein
impurity concentration of the second semiconductor region is 1×10 18 to 1×10 19 cm −3 .
13. The semiconductor device according to claim 12 , wherein
impurity concentration of the first semiconductor region is less than 5×10 17 cm −3 .
14. The semiconductor device according to claim 1 , wherein
an another end portion of the plurality of trenches on the second direction contacts to the fourth semiconductor region.