IP Library Granted Patent US 12,525,579
Granted Patent B2
US 12,525,579 · App. 18/003,345 · Granted Jan 13, 2026

Semiconductor device and method for producing same

Inventors: Kohei Taniguchi (Tokyo, JP); Yoshinobu Ozaki (Tokyo, JP); Kei Itagaki (Tokyo, JP); Kazuhiro Yamamoto (Tokyo, JP); Kanami Nakamura (Tokyo, JP); Hiroki Hashimoto (Tokyo, JP)
H01L25/0657H01L23/3142H10B41/20H10B43/20H10B80/00
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Quick Facts
Patent No.
US 12,525,579
App. No.
18/003,345
Granted
Jan 13, 2026
Kind
B2
Abstract

A semiconductor device includes: a substrate; an adhesive member arranged on a surface of the substrate; a first chip stacked on the adhesive member with a first adhesive piece interposed therebetween; and a second chip stacked on the first chip with a second adhesive piece interposed therebetween. The adhesive member has a multilayer structure including a pair of surface layers formed of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers.

Claims (45)

1 . A semiconductor device, comprising:

a substrate;

an adhesive member arranged on or above a surface of the substrate, wherein the adhesive member has a multilayer structure including a pair of surface layers formed of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers;

a first chip stacked on the adhesive member with a first adhesive piece interposed therebetween, wherein the first adhesive piece contacts both the first chip and the adhesive member; and

a second chip stacked on the first chip with a second adhesive piece interposed therebetween.

2 . The semiconductor device according to claim 1 , further comprising:

a third chip on the surface of the substrate; and

a plurality of support pieces arranged around the third chip on the surface of the substrate,

wherein the adhesive member is supported above the surface of the substrate by the plurality of support pieces and covers the third chip.

3 . The semiconductor device according to claim 1 , wherein at least a part of a peripheral portion of the second chip protrudes laterally from the first chip.

4 . The semiconductor device according to claim 1 ,

wherein in the multilayer structure of the adhesive member, the pair of surface layers and the intermediate layer are entirely aligned in a lateral direction of the semiconductor device, and

wherein at least a part of a peripheral portion of the first chip protrudes from the multilayer structure of the adhesive member in the lateral direction.

5 . The semiconductor device according to claim 1 , wherein the intermediate layer is a polyimide layer.

6 . The semiconductor device according to claim 1 , wherein the intermediate layer is a metal layer.

7 . The semiconductor device according to claim 1 , wherein the semiconductor device is a three-dimensional NAND memory.

8 . The semiconductor device according to claim 1 , wherein the pair of surface layers included in the multilayer structure are formed of cured products of the same thermosetting resin composition.

9 . The semiconductor device according to claim 1 , wherein the pair of surface layers of the adhesive member includes a first surface layer that contacts the substrate and a second surface layer that contacts the first adhesive piece.

10 . A semiconductor device manufacturing method, comprising:

arranging an adhesive member on or above a surface of a substrate, wherein the adhesive member has a multilayer structure including a pair of surface layers formed of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers, and wherein the pair of surface layers includes a first surface layer facing the substrate and a second surface layer facing away from the substrate;

stacking a first chip on the adhesive member with a first adhesive piece interposed therebetween, wherein the first adhesive piece contacts the first chip and the second surface layer of the adhesive member;

stacking a second chip on the first chip with a second adhesive piece interposed therebetween; and

curing the adhesive member, the first adhesive piece, and the second adhesive piece.

11 . The semiconductor device manufacturing method according to claim 10 , wherein the pair of surface layers included in the multilayer structure are formed of the same thermosetting resin composition.

12 . The semiconductor device manufacturing method according to claim 10 ,

wherein the first and second adhesive pieces are formed of a thermosetting resin composition, and

wherein the adhesive member, the first adhesive piece, and the second adhesive piece are collectively cured.

13 . The semiconductor device manufacturing method according to claim 10 , further comprising

arranging a third chip on the surface of the substrate; and

arranging a plurality of support pieces around the third chip on the surface of the substrate,

wherein the adhesive member is arranged to be supported by the plurality of support pieces above the surface of the substrate, and to cover the third chip.

14 . A semiconductor device, comprising:

a substrate;

an adhesive member arranged above a surface of the substrate, wherein the adhesive member has a multilayer structure including a pair of surface layers formed of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers;

a first chip stacked on the adhesive member with a first adhesive piece interposed therebetween;

a second chip stacked on the first chip with a second adhesive piece interposed therebetween;

a third chip arranged on the surface of the substrate; and

a plurality of support pieces arranged around the third chip on the surface of the substrate, wherein the adhesive member is supported by the plurality of support pieces and covers the third chip.

15 . The semiconductor device according to claim 14 ,

wherein at least a part of a peripheral portion of the second chip with the second adhesive piece protrudes laterally from the adhesive member.

16 . The semiconductor device according to claim 14 , wherein the intermediate layer is a polyimide layer.

17 . The semiconductor device according to claim 14 , wherein the intermediate layer is a metal layer.

18 . The semiconductor device according to claim 14 , wherein the semiconductor device is a three-dimensional NAND memory.

19 . The semiconductor device according to claim 14 , wherein the pair of surface layers included in the multilayer structure are formed of cured products of the same thermosetting resin composition.

20 . The semiconductor device according to claim 14 , wherein the pair of surface layers of the adhesive member includes a first surface layer that faces the substrate and a second surface layer that contacts the first adhesive piece.

Assignments (3)
CHANGE OF ADDRESS Recorded Feb 9, 2024
From: RESONAC CORPORATION
To: RESONAC CORPORATION
Reel/Frame 066547/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2023
From: TANIGUCHI, KOHEI; OZAKI, YOSHINOBU; ITAGAKI, KEI; YAMAMOTO, KAZUHIRO; NAKAMURA, KANAMI; HASHIMOTO, HIROKI
To: RESONAC CORPORATION
Reel/Frame 063678/0885 →
CHANGE OF NAME Recorded Apr 11, 2023
From: SHOWA DENKO MATERIALS CO., LTD.
To: RESONAC CORPORATION
Reel/Frame 063284/0307 →
Priority Claims (1)
JP 2020-115568 · Jul 3, 2020 · national
Continuity (1)
Related Publication 20230253366A1 · Aug 10, 2023
References Cited (15)
US 20100219507A1 · Misumi · 2010 [cited by examiner]
US 20130062758A1 · Imoto · 2013 [cited by examiner]
US 20140167291A1 · Nam · 2014 [cited by examiner]
JP 2010024427 · 2010 [cited by applicant]
JP 2014053538 · 2014 [cited by applicant]
KR 1020080020396 · 2008 [cited by applicant]
TW 200634935 · 2006 [cited by applicant]
TW 200725918 · 2007 [cited by applicant]
TW 201221614 · 2012 [cited by applicant]
TW I575670 · 2017 [cited by applicant]
WO 2005103180 · 2005 [cited by applicant]
WO 2020100308 · 2020 [cited by applicant]
WO 2020218523 · 2020 [cited by applicant]
International Search Report dated Sep. 14, 2021 for PCT/JP2021/024974. [cited by applicant]
International Preliminary Report on Patentability with Written Opinion dated Jan. 12, 2023 for PCT/JP2021/024974. [cited by applicant]