Three-dimensional flash memory using ferroelectric layer on basis of back gate structure
Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure. According to an embodiment, a three-dimensional flash memory comprises: a plurality of word liens extending on a substrate in a horizontal direction and sequentially stacked; and a plurality of strings extending through the plurality of word lines on the substrate in one direction, each of the plurality of strings including a channel layer extending in the one direction and a ferroelectric layer extending in the one direction to surround the channel layer, wherein a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed inside the channel layer, and the channel layer and the ferroelectric layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the ferroelectric layer is formed of a ferroelectric material and used as data storage by changing and maintaining the states of electric charges.
1 . A three-dimensional flash memory comprising:
a plurality of word lines extending in a horizontal direction on a substrate and sequentially stacked; and
a plurality of strings extending in one direction on the substrate through the plurality of word lines, each of the plurality of strings including
a channel layer extending in the one direction and a ferroelectric layer extending in the one direction to surround the channel layer, and
a back gate extending in the one direction and an insulating film extending in the one direction to surround the back gate being arranged inside the channel layer,
wherein the channel layer and the ferroelectric layer constitute one memory cell of a plurality of memory cells corresponding to the plurality of word lines,
wherein the ferroelectric layer is configured to store data by changing and maintaining states of charges while being formed of a ferroelectric material, and
wherein, in an erasure operation associated with a target memory cell of the plurality of memory cells in a selected string among the plurality of strings, the plurality of word lines are configured to receive an erase voltage, a bit line of the selected string is configured to receive a ground voltage, the back gate of the target memory cell is configured to be in a floating state, and the back gate of at least memory cell of the plurality of memory cells in a non-selected string among the plurality of strings adjacent to the selected string is configured to receive a pass voltage.
2 . The three-dimensional flash memory of claim 1 , wherein the back gate is configured to apply a voltage for changing and maintain the states of charges of the ferroelectric layer in a memory operation of the three-dimensional flash memory.
3 . The three-dimensional flash memory of claim 2 , wherein the back gate, which is included in each of the plurality of strings, is configured to receive the pass voltage that allows only the target memory cell to be programmed during a program operation of the three-dimensional flash memory based on application of a negative program voltage to a word line corresponding to the target memory cell subjected to the program operation among the plurality of word lines and voltages applied to a plurality of bit lines respectively connected to the plurality of strings.
4 . The three-dimensional flash memory of claim 3 , wherein, during the program operation, at least one word line corresponding to at least one other memory cell except for the target memory cell among the plurality of word lines is configured to float based on application of the pass voltage to the back gate.
5 . The three-dimensional flash memory of claim 2 , wherein, during a reading operation of the three-dimensional flash memory:
the back gate, which is included in the selected string including the target memory cell, is configured to receive a negative voltage at which only the target memory cell is read that is subjected to the reading operation among the plurality of strings based on application of a reading voltage to a word line corresponding to the target memory cell among the plurality of word lines;
to at least one word line corresponding to at least one other memory cell except for the target memory cell among the plurality of word lines is configured to receive the pass voltage; and
the bit line connected to the selected string is configured to receive a voltage.
6 . The three-dimensional flash memory of claim 2 , wherein, during a reading operation of the three-dimensional flash memory:
the back gate, which is included in the selected string including the target memory cell that is subjected to the reading operation among the plurality of strings, is configured to float so that only the target memory cell is read based on application of a reading voltage to a word line corresponding to the target memory cell among the plurality of word lines;
at least one word line corresponding to at least one other memory cell except to the target memory cell among the plurality of word lines is configured to receive the pass voltage; and
the bit line connected to the selected string is configured to receive a voltage.
7 . The three-dimensional flash memory of claim 5 ,
wherein at least one back gate, which is included in at least one non-selected string except for the selected string among the plurality of strings during the reading operation based on application of the reading voltage to the word line corresponding to the target memory cell among the plurality of word lines, is configured to receive the pass voltage that prevents memory cells included in the at least one non-selected string from being read, and
wherein at least one word line corresponding to at least one other memory cell except for the target memory cell among the plurality of word lines is configured to receive the pass voltage, and
wherein at least one bit line connected to the at least one non-selected string is configured to receive the voltage.
8 . The three-dimensional flash memory of claim 2 , wherein the insulating film has a same Equivalent Oxide Thickness (EOT) as an EOT of the ferroelectric layer.
9 . The three-dimensional flash memory of claim 8 , wherein, during a reading operation of the three-dimensional flash memory:
the back gate, which is included in the selected string including the target memory cell that is subjected to the reading operation among the plurality of strings based on application of a reading voltage to a word line corresponding to the target memory cell among the plurality of word lines, is configured to receive the reading voltage at which only the target memory cell is read;
at least one word line corresponding to at least one other memory cell except for the target memory cell among the plurality of word lines is configured to receive the pass voltage; and
the bit line connected to the selected string is configured to receive a voltage.