Silicon carbide semiconductor device
A super junction layer alternately has a first region and a second region. An element layer is provided above the super junction layer. The first region has a first portion and a second portion located between the first portion and a first main surface. The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface. In a cross section perpendicular to the second main surface and parallel to a direction from the first region toward the second region, a width of the second portion is larger than a width of the first portion, a width of the fourth portion is smaller than a width of the third portion.
1 . A silicon carbide semiconductor device comprising:
a substrate composed of a silicon carbide semiconductor having a first conductivity type;
a super junction layer that is provided above a first main surface of the substrate and that alternately has a first region having the first conductivity type and a second region having a second conductivity type;
an element layer provided above the super junction layer, the element layer comprising a first impurity region having the first conductivity type;
a first electrode provided on the element layer; and
a second electrode provided on a second main surface of the substrate opposite to the first main surface, wherein
the element layer is provided with a trench that has a bottom portion constituted of the first impurity region,
a gate electrode is provided inside the trench,
a connection region having the second conductivity type is in contact with the second region and the first impurity region,
the first impurity region separates the gate electrode from the connection region, the first region has a first portion and a second portion located between the first portion and the first main surface,
the second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface, and
in a cross section perpendicular to the second main surface and parallel to a direction from the first region toward the second region,
a width of the second portion is larger than a width of the first portion and is monotonously increased in a direction from the first portion toward the first main surface,
a width of the fourth portion is smaller than a width of the third portion and is monotonously decreased in a direction from the third portion toward the first main surface,
a total value of the width of the first portion and the width of the third portion is 0.5 μm or more and 4 μm or less, and
a height of each of the first region and the second region is 2 μm or more.
2 . The silicon carbide semiconductor device according to claim 1 , wherein
in the cross section perpendicular to the second main surface and parallel to the direction from the first region toward the second region,
the width of the first portion is smaller than a height of the first portion, and
the width of the third portion is smaller than a height of the third portion.
3 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration in the third portion is higher than an impurity concentration in the fourth portion.
4 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of each of the first portion and the third portion is 3×10 16 cm −3 or more and 5×10 17 cm −3 or less.
5 . The silicon carbide semiconductor device according to claim 1 , wherein a buffer layer having the first conductivity type is provided between the super junction layer and the substrate.
6 . The silicon carbide semiconductor device according to claim 1 , wherein
the element layer further includes a second impurity region in contact with the first impurity region and having the second conductivity type, and a third impurity region separated from the first impurity region by the second impurity region and having the first conductivity type,
the trench further has a side surface constituted of each of the first impurity region, the second impurity region, and the third impurity region,
the bottom portion of the trench is contiguous to the side surface, and
the second electrode is a source electrode, and the first electrode is a drain electrode.
7 . The silicon carbide semiconductor device according to claim 1 , wherein the first main surface corresponds to a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane.
8 . A silicon carbide semiconductor device, comprising:
a substrate composed of a silicon carbide semiconductor having a first conductivity type;
a super junction layer that is provided above a first main surface of the substrate and that alternately has a plurality of first regions having the first conductivity type and a plurality of second regions having a second conductivity type, the first regions being stacked together, the second regions being stacked together;
an element layer provided above the super junction layer;
a first electrode provided on the element layer; and
a second electrode provided on a second main surface of the substrate opposite to the first main surface, wherein
wherein each of the first regions has a first portion and a second portion located between the first portion and the first main surface,
wherein each of the second regions has a third portion and a fourth portion, the third portion being in contact with the first portion, and the fourth portion being in contact with the second portion and located between the third portion and the first main surface, and
wherein, in a cross section perpendicular to the second main surface and parallel to a direction from the first regions toward the second regions,
a width of the second portion is larger than a width of the first portion and is monotonously increased in a direction from the first portion toward the first main surface,
a width of the fourth portion is smaller than a width of the third portion and is monotonously decreased in a direction from the third portion toward the first main surface,
a total value of the width of the first portion and the width of the third portion is 0.5 μm or more and 4 μm or less, and
a height of each of the first regions and each of the second regions is 2 μm or more.
9 . The silicon carbide semiconductor device according to claim 8 , wherein the element layer comprises a first impurity region having the first conductivity layer,
wherein the element layer is provided with a trench that has a bottom portion constituted of the first impurity region,
wherein a gate electrode is provided inside the trench,
wherein a connection region having the second conductivity type is in contact with the multiple second regions and the first impurity region, and
wherein the first impurity region separates the gate electrode from the connection region.
10 . The silicon carbide semiconductor device according to claim 1 , wherein the connection region is in contact with the third portion of the second region.
11 . The silicon carbide semiconductor device according to claim 9 , wherein the connection region is in contact with one of the third portions of the multiple second regions.