Semiconductor device
A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.
1. A semiconductor device comprising:
a SiC semiconductor substrate of a first conductivity type;
a SiC epitaxial layer of the first conductivity type provided on the SiC semiconductor substrate and having an impurity concentration lower than that of the SiC semiconductor substrate;
a first semiconductor layer provided as a part of the SiC epitaxial layer and including first semiconductor pillars of the first conductivity type and second semiconductor pillars of a second conductivity type which extend in a first direction and are arranged alternately and repeatedly in a main surface of the SiC semiconductor substrate;
a second semiconductor layer of the first conductivity type, which is a layer other than the first semiconductor layer in the SiC epitaxial layer and located between the SiC semiconductor substrate and the first semiconductor layer;
a device active region provided on a main surface of the first semiconductor layer;
a termination region provided on the main surface of the first semiconductor layer and surrounding the device active region;
a channel stopper region of the first conductivity type provided on the main surface of the first semiconductor layer, surrounding the termination region, and having an impurity concentration higher than that of the SiC epitaxial layer; and
a plurality of first chip end portions parallel to a second direction intersecting with the first direction and a plurality of second chip end portions parallel to the first direction, the first chip end portions and the second chip end portions being provided so as to define a quadrilateral semiconductor chip,
wherein the first chip end portion includes a first side surface having a height of a cross-section from the first semiconductor layer to a middle of the second semiconductor layer and a second side surface having a height from the middle of the second semiconductor layer to a back surface of the semiconductor substrate, and
in the first chip end portion, a surface of the first side surface is covered with an impurity region of the first conductivity type having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.
2. The semiconductor device according to claim 1 ,
wherein the plurality of first chip end portions each have a bottom surface which connects a lower portion of the first side surface and an upper portion of the second side surface and has a horizontal plane in the second semiconductor layer, and
at least the first side surface and the bottom surface are covered with the impurity region.
3. The semiconductor device according to claim 2 ,
wherein the first side surface is tapered.
4. The semiconductor device according to claim 2 ,
wherein the SiC epitaxial layer includes a first epitaxial layer serving as an upper layer and a second epitaxial layer serving as a lower layer and having an impurity concentration half or lower than that of the first epitaxial layer, and
the first semiconductor pillars are substantially formed of the first epitaxial layer.
5. The semiconductor device according to claim 3 ,
wherein an angle of the first side surface is 80 degrees or less based on a horizontal plane.
6. The semiconductor device according to claim 2 ,
wherein the channel stopper region is in contact with the first semiconductor pillars and the second semiconductor pillars at the first chip end portions.
7. The semiconductor device according to claim 2 ,
wherein a MOSFET is formed in the device active region.
8. The semiconductor device according to claim 3 ,
wherein the SiC epitaxial layer includes a first epitaxial layer serving as an upper layer and a second epitaxial layer serving as a lower layer and having an impurity concentration half or lower than that of the first epitaxial layer, and
the first semiconductor pillars are substantially formed of the first epitaxial layer.
9. The semiconductor device according to claim 3 ,
wherein the channel stopper region is in contact with the first semiconductor pillars and the second semiconductor pillars at the first chip end portions.
10. The semiconductor device according to claim 4 ,
wherein the channel stopper region is in contact with the first semiconductor pillars and the second semiconductor pillars at the first chip end portions.
11. The semiconductor device according to claim 3 ,
wherein a MOSFET is formed in the device active region.
12. The semiconductor device according to claim 4 ,
wherein a MOSFET is formed in the device active region.