Display substrate, manufacturing method therefor, and display device
A display substrate, a manufacturing method therefor, and a display device are provided. The display substrate includes a base substrate and at least one transistor disposed on the base substrate, with a transistor including an active layer pattern disposed on the base substrate; a first source-drain electrode disposed on the base substrate and electrically connected with the active layer pattern; a first gate electrode disposed on a side of the active layer pattern away from the base substrate, the first gate electrode and the active layer pattern having overlapped orthographic projections on the base substrate and are not in contact with each other; a second source-drain electrode disposed on a side of the active lay pattern away from the base substrate and including a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern, the second sub-electrode and the active layer pattern have overlapped orthographic projections on the base substrate and are not in contact with each other.
1 . A display substrate comprising: a base substrate and at least one transistor disposed on the base substrate; the at least one transistor comprises:
an active layer pattern disposed on the base substrate;
a first source-drain electrode disposed on the base substrate, with the first source-drain electrode being electrically connected with the active layer pattern;
a first gate electrode disposed on a side of the active layer pattern away from the base substrate, wherein orthographic projections of the first gate electrode and the active layer pattern on the base substrate are overlapped with each other and the first gate electrode and the active layer pattern are not in contact with each other;
a second source-drain electrode disposed on the side of the active layer pattern away from the base substrate, the second source-drain electrode comprises a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern, orthographic projections of the second sub-electrode and the active layer pattern on the base substrate are overlapped with each other and the second sub-electrode and the active layer pattern are not in contact with each other,
wherein the display substrate further comprises: a signal line electrically connected with the first source-drain electrode, and
the signal line is located between the first source-drain electrode and the base substrate, and the display substrate further comprises a buffer layer, the buffer layer is located between the signal line and the active layer pattern, a third via is provided in the buffer layer, and the first source-drain electrode is electrically connected with the signal line through the third via.
2 . The display substrate according to claim 1 , wherein the second source-drain electrode further comprises a third sub-electrode located on a side of the first sub-electrode away from the first gate electrode, and orthographic projections of the third sub-electrode and the active layer pattern on the base substrate are overlapped with each other and the third sub-electrode and the active layer pattern are not in contact with each other.
3 . The display substrate according to claim 2 , wherein the transistor further comprises a first insulating layer, the first insulating layer is positioned between the active layer pattern and the first gate electrode, the first insulating layer covers the active layer pattern, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, a first via and a second via are provided in the first insulating layer, the first source-drain electrode is electrically connected with the active layer pattern through the first via, and the second source-drain electrode is electrically connected with the active layer pattern through the second via.
4 . The display substrate according to claim 2 , wherein the transistor further comprises a first insulating layer, the first insulating layer comprises at least one insulating layer pattern, the at least one insulating layer pattern covers a part of the active layer pattern, and there is a non-overlapping region between an orthographic projection of the at least one insulating layer pattern and an orthographic projection of at least part of the active layer pattern on the base substrate, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, and the first source-drain electrode and the second source-drain electrode are electrically connected with the non-overlapping region of the active layer pattern respectively.
5 . The display substrate according to claim 1 , wherein the first sub-electrode and the second sub-electrode are integrally formed.
6 . The display substrate according to claim 5 , wherein the transistor further comprises a first insulating layer, the first insulating layer is positioned between the active layer pattern and the first gate electrode, the first insulating layer covers the active layer pattern, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, a first via and a second via are provided in the first insulating layer, the first source-drain electrode is electrically connected with the active layer pattern through the first via, and the second source-drain electrode is electrically connected with the active layer pattern through the second via.
7 . The display substrate according to claim 5 , wherein the transistor further comprises a first insulating layer, the first insulating layer comprises at least one insulating layer pattern, the at least one insulating layer pattern covers a part of the active layer pattern, and there is a non-overlapping region between an orthographic projection of the at least one insulating layer pattern and an orthographic projection of at least part of the active layer pattern on the base substrate, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, and the first source-drain electrode and the second source-drain electrode are electrically connected with the non-overlapping region of the active layer pattern respectively.
8 . The display substrate according to claim 1 , wherein the first source-drain electrode comprises a fourth sub-electrode and a fifth sub-electrode connected with each other, the fifth sub-electrode is located on a side of the fourth sub-electrode away from the first gate electrode, the fourth sub-electrode is electrically connected with the active layer pattern, and orthographic projections of the fifth sub-electrode and the active layer pattern on the base substrate are overlapped with each other and the fifth sub-electrode and the active layer pattern are not in contact with each other.
9 . The display substrate according to claim 8 , wherein the transistor further comprises a first insulating layer, the first insulating layer is positioned between the active layer pattern and the first gate electrode, the first insulating layer covers the active layer pattern, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, a first via and a second via are provided in the first insulating layer, the first source-drain electrode is electrically connected with the active layer pattern through the first via, and the second source-drain electrode is electrically connected with the active layer pattern through the second via.
10 . The display substrate according to claim 1 , wherein the transistor further comprises a first insulating layer, the first insulating layer is positioned between the active layer pattern and the first gate electrode, the first insulating layer covers the active layer pattern, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, a first via and a second via are provided in the first insulating layer, the first source-drain electrode is electrically connected with the active layer pattern through the first via, and the second source-drain electrode is electrically connected with the active layer pattern through the second via.
11 . The display substrate according to claim 1 , wherein the transistor further comprises a first insulating layer, the first insulating layer comprises at least one insulating layer pattern, the at least one insulating layer pattern covers a part of the active layer pattern, and there is a non-overlapping region between an orthographic projection of the at least one insulating layer pattern and an orthographic projection of at least part of the active layer pattern on the base substrate, the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on a side of the first insulating layer away from the base substrate, and the first source-drain electrode and the second source-drain electrode are electrically connected with the non-overlapping region of the active layer pattern respectively.
12 . The display substrate according to claim 1 , further comprising a pixel electrode disposed on a side of the transistor away from the base substrate, the pixel electrode and the second source-drain electrode are integrally formed.
13 . The display substrate according to claim 1 , wherein the first source-drain electrode and the active layer pattern are integrally formed.
14 . The display substrate according to claim 1 , wherein the first source-drain electrode and the active layer pattern are integrally formed and the signal line is located on a side of the first source-drain electrode close to the base substrate, or the signal line is located on a side of the first source-drain electrode away from the base substrate.
15 . The display substrate according to claim 1 , wherein the material of the active layer pattern is made of an oxide semiconductor.
16 . The display substrate according to claim 1 , wherein the transistor is configured as a transistor in a gate driving circuit.
17 . A display device comprising the display substrate according to claim 1 .
18 . A method for manufacturing a display substrate, comprising:
forming an active layer pattern on a base substrate;
forming a first source-drain electrode on the base substrate so that at least a part of the first source-drain electrode is electrically connected with the active layer pattern;
forming a first gate electrode on a side of the active layer pattern away from the base substrate, so that orthographic projections of the first gate electrode and the active layer pattern on the base substrate are overlapped with each other and the first gate electrode and the active layer pattern are not in contact with each other;
forming a second source-drain electrode on the side of the active layer pattern away from the base substrate, the second source-drain electrode comprises a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern, and orthographic projections of the second sub-electrode and the active layer pattern on the base substrate are overlapped with each other and the second sub-electrode and the active layer pattern are not in contact with each other,
wherein the method further comprises: electrically connecting a signal line with the first source-drain electrode, and
the signal line is located between the first source-drain electrode and the base substrate, and the display substrate further comprises a buffer layer, the buffer layer is located between the signal line and the active layer pattern, a third via is provided in the buffer layer, and the first source-drain electrode is electrically connected with the signal line through the third via.