Circuit board
An antenna substrate according to the embodiment includes a substrate; an antenna pattern layer on the substrate; a first insulating layer including a resin and an inorganic filler on the substrate and the antenna pattern layer; and a second insulating layer including a resin and an inorganic filler on the first insulating layer, and wherein the second insulating layer has a higher dielectric constant and thickness than the first insulating layer.
1 . An antenna substrate comprising:
a substrate;
an uppermost conductive pattern layer disposed on the substrate;
a first solder resist layer disposed on the uppermost conductive pattern layer; and
a second solder resist layer disposed on the first solder resist layer,
wherein the first solder resist layer includes a material different from a material of the second solder resist layer,
wherein the first solder resist layer includes a first region disposed on the substrate and not overlapping the uppermost conductive pattern layer in a vertical direction, and a second region disposed on the uppermost conductive pattern layer and having a thickness smaller than a thickness of the first region,
wherein a thickness of the second solder resist layer is greater than the thickness of the first region of the first solder resist layer,
wherein the second solder resist layer does not contact the uppermost conductive pattern layer and is spaced apart from the uppermost conductive pattern layer by the thickness of the second region in the vertical direction,
wherein the uppermost conductive pattern layer includes a plurality of conductive patterns spaced apart from each other in a horizontal direction,
wherein the second solder resist layer includes a plurality of insulating patterns overlapping each of the plurality of conductive patterns in the vertical direction and spaced apart from each other in the horizontal direction, and
wherein a width of each of the plurality of insulating patterns in the horizontal direction is greater than a width of each of the plurality of conductive patterns in the horizontal direction.
2 . The antenna substrate of claim 1 , wherein a dielectric constant of the second solder resist layer is greater than a dielectric constant of the first solder resist layer.
3 . The antenna substrate of claim 2 , wherein the second solder resist layer has a dielectric constant of 3 to 6 times a dielectric constant of the first solder resist layer.
4 . The antenna substrate of claim 1 , wherein a thickness of the second solder resist layer is 1.5 to 5 times the thickness of the first solder resist layer.
5 . The antenna substrate of claim 1 , wherein a thickness of the uppermost conductive pattern layer is thinner than the thickness of the first solder resist layer and the second solder resist layer.
6 . The antenna substrate of claim 1 , wherein the uppermost conductive pattern layer is a dual resonance antenna pattern layer resonating in each of different frequency bands.
7 . The antenna substrate of claim 6 , wherein the uppermost conductive pattern layer resonates in each of a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz.
8 . The antenna substrate of claim 1 , wherein the second solder resist layer has a thickness of 25 μm to 65 μm.
9 . The antenna substrate of claim 8 , wherein the first solder resist layer has a thickness of 10 μm to 20 μm.
10 . The antenna substrate of claim 1 , wherein the second solder resist layer includes at least one from a group consisting of TiO 2 , Al 2 O 3 , BaTiO 3 and CaTiO 3 .
11 . The antenna substrate of claim 10 , wherein the second solder resist layer further includes a SiO 2 .
12 . The antenna substrate of claim 10 , wherein the first solder resist layer includes a SiO 2 .
13 . The antenna substrate of claim 3 , wherein the dielectric constant of the first solder resist layer satisfies a range of 3 to 5.
14 . The antenna substrate of claim 3 , wherein the dielectric constant of the second solder resist layer satisfies a range of 15 to 20.
15 . The antenna substrate of claim 4 , wherein the thickness of the first solder resist layer is a thickness of a region vertically overlapping the uppermost conductive pattern layer.