Circuit board
A circuit board according to an embodiment includes an insulating layer including first to third regions; an outer circuit pattern disposed on upper surfaces of the first to third regions of the insulating layer, and a solder resist including a first part disposed on the first region of the insulating layer, a second part disposed on the second region, and a third part disposed on the third region, wherein the outer circuit pattern includes a first trace disposed on an upper surface of the first region of the insulating layer; a first pad disposed on an upper surface of the first region of the insulating layer; and a second trace disposed on an upper surface of the third region of the insulating layer; wherein an upper surface of the first part of the solder resist is positioned lower than an upper surface of the first trace; and a height of the first trace is different from a height of the first pad.
1 . A circuit board comprising:
a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction;
an outer circuit pattern disposed on the build-up insulating layer; and
a protective layer disposed on the build-up insulating layer,
wherein the protective layer includes a first part and a second part having a thickness greater than that of the first part,
wherein the outer circuit pattern includes a first pad and a first trace penetrating the first part of the protective layer,
wherein the first pad and the first trace have different thicknesses,
wherein the thickness of the first pad is smaller than the thickness of the first part of the protective layer, and
wherein the first pad does not overlap the protective layer in the vertical direction.
2 . The circuit board of claim 1 , wherein an upper surface of the first pad is positioned lower than an upper surface of the first trace.
3 . The circuit board of claim 1 , wherein the first pad is provided in plurality on the build-up insulating layer, and
wherein the first trace is disposed in a region between the plurality of first pads.
4 . The circuit board of claim 3 , wherein a width of the first pad in a horizontal direction is greater than a width of the first trace in the horizontal direction.
5 . The circuit board of claim 1 , wherein the first part of the protective layer is provided with a same height around each of a side surface of the first pad and a side surface of the first trace.
6 . The circuit board of claim 5 , wherein an upper surface of the first pad is positioned lower than the first part of the protective layer, and
wherein an upper surface of the first trace is positioned higher than the first part of the protective layer.
7 . The circuit board of claim 6 , wherein the second part of the protective layer is positioned higher than the upper surfaces of the first pad and the first trace.
8 . The circuit board of claim 1 , wherein an upper surface of the first pad includes a curved surface.
9 . The circuit board of claim 1 , wherein a height of the first part of the protective layer satisfies a range of 70% to 85% of a height of the first trace, and
wherein a height of the first pad satisfies a range of 70% to 99% of the height of the first part.
10 . The circuit board of claim 1 , wherein the outer circuit pattern further includes a second trace overlapping the second part of the protective layer in the vertical direction, and
wherein a height of the second trace corresponds to a height of the first trace.
11 . The circuit board of claim 10 , wherein the outer circuit pattern further includes a second pad partially overlapping the second part of the protective layer in the vertical direction; and
wherein the protective layer includes an opening overlapping an upper surface of the second pad in the vertical direction.
12 . The circuit board of claim 11 , wherein the upper surface of the second pad includes a first portion that does not overlap with the opening in the vertical direction and a second portion that does not overlap with the opening in the vertical direction, and
wherein the first portion has a step with the second portion.
13 . The circuit board of claim 12 , wherein the first portion of the second pad is positioned higher than the second portion of the second pad.
14 . The circuit board of claim 13 , wherein a height of the first portion of the second pad corresponds to a height of the first trace.
15 . The circuit board of claim 13 , wherein a height of the second portion of the second pad corresponds to a height of the first pad.
16 . A semiconductor package comprising:
a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction;
an outer circuit pattern disposed on the build-up insulating layer;
a protective layer disposed on the build-up insulating layer; and
an adhesive part disposed on the outer circuit pattern,
wherein the protective layer includes a first part and a second part having a thickness greater than that of the first part,
wherein the outer circuit pattern includes a first pad and a first trace penetrating the first part of the protective layer,
wherein the first pad and the first trace have different thicknesses,
wherein the thickness of the first pad is smaller than the thickness of the first part of the protective layer, and
wherein the first pad does not overlap the protective layer in the vertical direction.
17 . The semiconductor package of claim 16 , wherein an upper surface of the first pad is positioned lower than an upper surface of the first trace, and
wherein the upper surface of the first trace is higher than a lower surface of the adhesive part.
18 . The semiconductor package of claim 16 , wherein the first part of the protective layer is provided with the same height around each of a side surface of the first pad and a side surface of the first trace,
wherein an upper surface of the first pad is positioned lower than the first part of the protective layer,
wherein an upper surface of the first trace is positioned higher than the first part of the protective layer, and
wherein the second part of the protective layer is positioned higher than the upper surfaces of each of the first pad and the first trace.
19 . The semiconductor package of claim 16 , wherein an upper surface of the first pad includes a curved surface contacting a lower surface of the adhesive part.
20 . The semiconductor package of claim 16 , wherein the outer circuit pattern further includes a second pad partially overlapping the second part of the protective layer in the vertical direction,
wherein the protective layer includes an opening overlapping an upper surface of the second pad in the vertical direction,
wherein an upper surface of the second pad includes a first portion that does not overlap with the opening in the vertical direction and a second portion that does not overlap with the opening in the vertical direction and has a step with the first portion, and
wherein the adhesive part includes a second adhesive member disposed on the second portion of the second pad.