Method and system for processing instruction timeout, and device and medium
View Patent ↗Disclosed are a method and system for processing an instruction timeout, a device and a storage medium. The method includes: in response to a timeout of an original instruction sent by a host end reaching a first threshold value, sending an abort instruction, and detecting whether the abort instruction times out; in response to the abort instruction timing out and the timeout of the original instruction reaching a second threshold value, sending a reset instruction to reset a target end; in response to the reset instruction timing out and the timeout of the original instruction reaching a maximum threshold value, removing the target end, and determining whether the original instruction is blocked at the target end; and in response to the original instruction not being blocked at the target end, returning an instruction error prompt to the host end.
1. A method for processing an instruction timeout, comprising:
in response to a timeout of an original instruction sent by a host end reaching a first threshold value, sending an abort instruction, and detecting whether the abort instruction times out;
in response to the abort instruction timing out and the timeout of the original instruction reaching a second threshold value, sending a reset instruction to reset a target end;
in response to the reset instruction timing out and the timeout of the original instruction reaching a maximum threshold value, removing the target end, and determining whether the original instruction is blocked at the target end; and
in response to the original instruction not being blocked at the target end, returning an instruction error prompt to the host end.
2. The method according to claim 1 , further comprising:
in response to the timeout of the original instruction reaching a baseline threshold value that is less than the first threshold value, determining whether a target device supports a detecting instruction; and
in response to the target device supporting the detecting instruction, sending the detecting instruction to the target device, to detect whether the original instruction is lost.
3. The method according to claim 2 , further comprising:
in response to the original instruction being lost, sending a second reset instruction to recover a target LUN of the target device.
4. The method according to claim 2 , further comprising:
in response to the target device not supporting the detecting instruction, sending a response instruction to the target device to test whether a target LUN is capable of making a response.
5. A computing device, comprising:
at least one processor; and
a memory, the memory storing computer instructions operable in the processor, and the instructions, when executed by the processor, implementing the steps of the method according to claim 1 .
6. A non-transitory computer-readable storage medium, storing computer-readable instructions, the computer-readable instructions, when executed by a processor, implementing the steps of the method according to claim 1 .
7. The method according to claim 2 , wherein the baseline threshold value, the first threshold value, the second threshold value, and the maximum threshold value increase in sequence.
8. The method according to claim 2 , wherein the method further comprises:
when the host end sends an instruction to a disk, by using a system, recording sending time of the instruction, and then regularly inquiring a status and time consumption of the instruction through a timer.
9. The method according to claim 8 , wherein the method further comprises:
when it is found that the original instruction exceeds the baseline threshold value for a first time, sending an otur instruction to check responsiveness of the disk and whether the original instruction is lost.
10. The computing device according to claim 5 , further comprising:
in response to the timeout of the original instruction reaching a baseline threshold value that is less than the first threshold value, determining whether a target device supports a detecting instruction; and
in response to the target device supporting the detecting instruction, sending the detecting instruction to the target device, to detect whether the original instruction is lost.
11. The computing device according to claim 10 , further comprising:
in response to the original instruction being lost, sending a second reset instruction to recover a target LUN of the target device.
12. The computing device according to claim 10 , further comprising:
in response to the target device not supporting the detecting instruction, sending a response instruction to the target device to test whether a target LUN is capable of making a response.
13. The non-transitory computer-readable storage medium according to claim 6 , further comprising:
in response to the timeout of the original instruction reaching a baseline threshold value that is less than the first threshold value, determining whether a target device supports a detecting instruction; and
in response to the target device supporting the detecting instruction, sending the detecting instruction to the target device, to detect whether the original instruction is lost.
14. The non-transitory computer-readable storage medium according to claim 13 , further comprising:
in response to the original instruction being lost, sending a second reset instruction to recover a target LUN of the target device.