IP Library Granted Patent US 10,360,033
Granted Patent B2
US 10,360,033 · App. 16/018,343 · Granted Jul 23, 2019

Conditional transaction end instruction

Inventors: Dan F. Greiner (San Jose, CA); Christian Jacobi (Poughkeepsie, NY); Marcel Mitran (Markham, CA); Donald W. Schmidt (Stone Ridge, NY); Timothy J. Slegel (Staatsburg, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F9/3005G06F9/3004G06F9/30043G06F9/30047G06F9/30072G06F9/30076G06F9/30087G06F9/30152G06F9/3802G06F9/3834G06F9/3859G06F9/467G06F9/30189
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,360,033
App. No.
16/018,343
Granted
Jul 23, 2019
Kind
B2
Abstract

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

Claims (50)

1. A computer program product for executing an instruction in a computing environment, said computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:

obtaining the instruction for execution, the instruction having associated therewith an operation code to specify a conditional transaction end operation; and

executing, by a processor, the instruction, the executing comprising:

determining whether the processor is in a nonconstrained transactional execution mode;

determining whether a transaction nesting depth is of a predefined value;

based on the processor being in the nonconstrained transactional execution mode and the transaction nesting depth being of the predefined value, fetching an operand from a location specified by the instruction;

based on the operand comprising one value, ending a transaction associated with the instruction; and

based on the operand comprising another value, delaying completion of the instruction until a predefined action occurs.

2. The computer program product of claim 1 , wherein based on the operand comprising a further value, transactional execution of the transaction is aborted.

3. The computer program product of claim 2 , wherein the further value comprises a negative value, the one value comprises zero, and the other value comprises a positive value.

4. The computer program product of claim 2 , wherein based on aborting the transactional execution, a condition code in a transaction abort program status word is set to a defined value.

5. The computer program product of claim 1 , wherein the instruction includes one or more fields to provide the location from which the operand is fetched.

6. The computer program product of claim 5 , wherein the one or more fields comprise an index field, a base field, a first displacement field and a second displacement field, wherein contents of registers designated by one or more of the index field and the base field are added to a concatenation of the second displacement field and the first displacement field to provide the location.

7. The computer program product of claim 1 , wherein the operand is stored by another processor or an input/output subsystem coupled to the processor.

8. The computer program product of claim 1 , wherein the predefined action comprises exceeding an interval of time, and wherein the executing further comprises:

aborting transactional execution of the transaction; and

setting a condition code in a transaction abort program status word to a defined value.

9. The computer program product of claim 1 , wherein based on ending the transaction, store accesses made by the transaction are committed, a transaction nesting depth is set to zero, the processor exits transactional execution mode, and a condition code is set to a defined value.

10. A computer system for executing an instruction in a computing environment, said computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:

obtaining the instruction for execution, the instruction having associated therewith an operation code to specify a conditional transaction end operation; and

executing, by the processor, the instruction, the executing comprising:

determining whether the processor is in a nonconstrained transactional execution mode:

determining whether a transaction nesting depth is of a predefined value;

based on the processor being in the nonconstrained transactional execution mode and the transaction nesting depth being of the predefined value, fetching an operand from a location specified by the instruction;

based on the operand comprising one value, ending a transaction associated with the instruction; and

based on the operand comprising another value, delaying completion of the instruction until a predefined action occurs.

11. The computer system of claim 10 , wherein based on the operand comprising a further value, transactional execution of the transaction is aborted.

12. The computer system of claim 10 , wherein the predefined action comprises exceeding an interval of time, and wherein the executing further comprises:

aborting transactional execution of the transaction; and

setting a condition code in a transaction abort program status word to a defined value.

13. The computer system of claim 10 , wherein based on ending the transaction, store accesses made by the transaction are committed, a transaction nesting depth is set to zero, the processor exits transactional execution mode, and a condition code is set to a defined value.

14. A computer-implemented method of executing an instruction in a computing environment, said computer-implemented method comprising:

obtaining the instruction for execution, the instruction having associated therewith an operation code to specify a conditional transaction end operation; and

executing, by a processor, the instruction, the executing comprising:

determining whether the processor is in a nonconstrained transactional execution mode;

determining whether a transaction nesting depth is of a predefined. value;

based on the processor being in the nonconstrained transactional execution mode and the transaction nesting depth being of the predefined value, fetching an operand from a location specified by the instruction;

based on the operand comprising one value, ending a transaction associated with the instruction; and

based on the operand comprising another value, delaying completion of the instruction until a predefined action occurs.

15. The computer-implemented method of claim 14 , wherein based on the operand comprising a further value, transactional execution of the transaction is aborted.

16. The computer-implemented method of claim 14 , wherein the predefined action comprises exceeding an interval of time, and wherein the executing further comprises:

aborting transactional execution of the transaction; and

setting a condition code in a transaction abort program status word to a defined value.

17. The computer-implemented method of claim 14 , wherein based on ending the transaction, store accesses made by the transaction are committed, a transaction nesting depth is set to zero, the processor exits transactional execution mode, and a condition code is set to a defined value.

18. The computer-implemented method of claim 14 , wherein the instruction includes one or more fields to provide the location from which the operand is fetched.

19. The computer system of claim 10 , wherein the instruction includes one or more fields to provide the location from which the operand is fetched.

20. The computer system of claim 10 , wherein the operand is stored by another processor or an input/output subsystem coupled to the processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2018
From: GREINER, DAN F.; JACOBI, CHRISTIAN; MITRAN, MARCEL; SCHMIDT, DONALD W.; SLEGEL, TIMOTHY J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046206/0825 →
Continuity (3)
Continuation 15228067 · Aug 4, 2016
Continuation 14212004 · Mar 14, 2014
Related Publication 20180300129A1 · Oct 18, 2018
Cited By (1)
US 12,254,320