Scan circuit, display apparatus, and method of operating scan circuit
A scan circuit is provided. The scan circuit includes a plurality of scan units in a plurality of stages, respectively. A respective scan unit of the plurality of scan units includes an output subcircuit. The output subcircuit includes a first switch transistor and a second switch transistor. A source electrode of the first switch transistor is coupled to a third terminal configured to receive a first clock signal. A drain electrode of the first switch transistor is coupled to a first output terminal configured to output a first control signal. A source electrode of the second switch transistor is coupled to a fourth terminal configured to receive the third clock signal. A drain electrode of the second switch transistor is coupled to a second output terminal configured to output a second control signal. Gate electrodes of the first switch transistor and the second switch transistor are coupled to a first node.
1. A scan circuit, comprising a plurality of scan subcircuits in a plurality of stages, respectively;
wherein a respective scan subcircuit of the plurality of scan subcircuits comprises an output subcircuit, and at least one of an input subcircuit, a first processing subcircuit, or a second processing subcircuit;
the respective scan subcircuit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal;
wherein the output subcircuit comprises a first output terminal, a second output terminal, a first switch transistor, and a second switch transistor;
a source electrode of the first switch transistor is coupled to a third terminal configured to receive the first clock signal;
a drain electrode of the first switch transistor is coupled to the first output terminal configured to output a first control signal;
a source electrode of the second switch transistor is coupled to a fourth terminal configured to receive the third clock signal;
a drain electrode of the second switch transistor is coupled to the second output terminal configured to output a second control signal; and
gate electrodes of the first switch transistor and the second switch transistor are coupled to a first node;
wherein the first processing subcircuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
source electrodes of the third transistor and the fourth transistor are coupled to a drain electrode of the fifth transistor;
drain electrodes of the third transistor and the fourth transistor are coupled to a third node;
a gate electrode of the third transistor is coupled to the third terminal configured to receive the first clock signal; and
a gate electrode of the fourth transistor is coupled to the fourth terminal configured to receive the third clock signal;
wherein a gate electrode of the fifth transistor and a drain electrode of the second transistor are coupled to a second node;
a source electrode of the fifth transistor is coupled to a fifth terminal configured to receive the first reference signal; and
a source electrode of the second transistor is coupled to a second terminal configured to receive the second reference signal.
2. The scan circuit of claim 1 , wherein the output subcircuit further comprises a first control transistor and a second control transistor;
a source electrode of the first control transistor and a source electrode of the second control transistor are coupled to a fifth terminal configured to receive the first reference signal;
a drain electrode of the first control transistor is coupled to the first output terminal;
a drain electrode of the second control transistor is coupled to the second output terminal; and
gate electrodes of the first control transistor and the second control transistor are coupled to a second node.
3. The scan circuit of claim 2 , wherein the output subcircuit further comprises an eleventh transistor coupled between the first control transistor and the first switch transistor;
a gate electrode of the eleventh transistor is coupled to the first node; and
at least one of a source electrode and a drain electrode of the eleventh transistor is coupled to the first output terminal.
4. The scan circuit of claim 3 , wherein both of the source electrode and the drain electrode of the eleventh transistor is coupled to the first output terminal.
5. The scan circuit of claim 2 , wherein the respective scan subcircuit further comprises a second capacitor;
a first capacitor electrode of the second capacitor is coupled to the source electrode of the first control transistor; and
a second capacitor electrode of the second capacitor is coupled to the second node.
6. The scan circuit of claim 1 , wherein the respective scan subcircuit further comprises a third capacitor;
a first capacitor electrode of the third capacitor is coupled to the first node; and
a second capacitor electrode of the third capacitor is coupled to a second terminal configured to receive a second reference signal.
7. The scan circuit of claim 1 , wherein the input subcircuit comprises an input transistor, a first transistor, an input terminal, and a first terminal;
a gate electrode of the input transistor and a source electrode of the first transistor are coupled to the first terminal configured to receive the second clock signal;
a gate electrode of the first transistor and a drain electrode of the input transistor are coupled to a third node;
a source electrode of the input transistor is coupled to the input terminal configured to receive a start signal or an output signal from a previous scan subcircuit of a previous stage; and
a drain electrode of the first transistor is coupled to a second node.
8. The scan circuit of claim 1 , wherein the second processing subcircuit comprises a seventh transistor and an eighth transistor;
a gate electrode of the seventh transistor is coupled to a fourth node;
a source electrode of the seventh transistor and a gate electrode of the eighth transistor are coupled to a sixth terminal configured to receive the fourth clock signal;
a drain electrode of the seventh transistor and a source electrode of the eighth transistor are coupled to a fifth node; and
a drain electrode of the eighth transistor is coupled to the first node.
9. The scan circuit of claim 1 , wherein the respective scan subcircuit further comprises a third processing subcircuit;
wherein the third processing subcircuit comprises a ninth transistor having a gate electrode coupled to a second node, a source electrode coupled to a sixth terminal configured to receive the fourth clock signal, and a drain electrode coupled to the first node.
10. A display apparatus, comprising a light emitting substrate and the scan circuit of claim 1 , the scan circuit configured to provide control signals to the light emitting substrate.
11. The display apparatus of claim 10 , comprising a plurality of subpixels;
wherein a respective subpixel of the plurality of subpixels comprises:
a first light emitting element;
a first pixel driving circuit configured to control light emission in the first light emitting element;
a second light emitting element; and
a second pixel driving circuit configured to control light emission in the second light emitting element;
wherein the first pixel driving circuit is configured to receive the first control signal output from the first output terminal; and
the second pixel driving circuit is configured to receive the second control signal output from the second output terminal.
12. The display apparatus of claim 11 , wherein the first light emitting element and the second light emitting element are configured to emit a light of a same color.
13. The display apparatus of claim 11 , further comprising a color filter substrate;
wherein the color filter substrate comprises:
a color conversion layer comprising a plurality of color conversion blocks; and
a color filter comprising a plurality of color filter blocks.
14. A scan circuit, comprising a plurality of scan subcircuits in a plurality of stages, respectively;
wherein a respective scan subcircuit of the plurality of scan subcircuits comprises an output subcircuit, and at least one of an input subcircuit, a first processing subcircuit, or a second processing subcircuit;
the respective scan subcircuit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal;
wherein the output subcircuit comprises a first output terminal, a second output terminal, a first switch transistor, and a second switch transistor;
a source electrode of the first switch transistor is coupled to a third terminal configured to receive the first clock signal;
a drain electrode of the first switch transistor is coupled to the first output terminal configured to output a first control signal;
a source electrode of the second switch transistor is coupled to a fourth terminal configured to receive the third clock signal;
a drain electrode of the second switch transistor is coupled to the second output terminal configured to output a second control signal; and
gate electrodes of the first switch transistor and the second switch transistor are coupled to a first node;
wherein the second processing subcircuit comprises a seventh transistor and an eighth transistor;
a gate electrode of the seventh transistor is coupled to a fourth node;
a source electrode of the seventh transistor and a gate electrode of the eighth transistor are coupled to a sixth terminal configured to receive the fourth clock signal;
a drain electrode of the seventh transistor and a source electrode of the eighth transistor are coupled to a fifth node; and
a drain electrode of the eighth transistor is coupled to the first node;
wherein the second processing subcircuit further comprises a sixth transistor and a first capacitor;
a gate electrode of the sixth transistor is coupled to a second terminal configured to receive the second reference signal;
a source electrode of the sixth transistor is coupled to a third node;
a drain electrode of the sixth transistor and a first capacitor electrode of the first capacitor are coupled to the fourth node; and
a second capacitor electrode of the first capacitor is coupled to the fifth node.
15. A method of operating a display apparatus comprising a light emitting substrate and a scan circuit configured to provide control signals to the light emitting substrate, comprising:
providing at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal to a respective scan subcircuit of a plurality of scan subcircuits of the scan circuit;
outputting an effective voltage of the first clock signal as a first control signal to the light emitting substrate; and
outputting an effective voltage of the third clock signal as a second control signal to the light emitting substrate;
wherein the first control signal and the second control signal are out of phase with respect to each other; and
the light emitting substrate comprises a plurality of subpixels, a respective subpixel of the plurality of subpixels comprising at least a main light emitting element driven by a main pixel driving circuit and at least an auxiliary light emitting element driven by an auxiliary pixel driving circuit;
wherein the method further comprises:
providing the first control signal to the main pixel driving circuit;
providing the second control signal to the auxiliary pixel driving circuit;
providing a first data signal to the main pixel driving circuit; and
providing a second data signal to the auxiliary pixel driving circuit;
wherein the first data signal and the second data signal are provided using a single data line connecting a source integrated circuit and the light emitting substrate.
16. The method of claim 15 , wherein outputting the first control signal and outputting the second control signal comprise:
providing the first clock signal to a source electrode of a first switch transistor;
providing the third clock signal to a source electrode of a second switch transistor; and
coupling gate electrodes of the first switch transistor and the second switch transistor to a first node.
17. The method of claim 15 , further comprising:
adjusting the third clock signal to have a constant ineffective voltage level; and
outputting an ineffective voltage of the third clock signal to the light emitting substrate.