Scan driver
A scan driver is disclosed that includes a plurality of stages for supplying scan signals to scan lines. A first stage among the stages includes: a first sub-stage circuit for generating a first scan signal, based on an input signal, a first clock signal, a second clock signal, a first power source, and a second power source; and a first charge pump circuit for supplying a bias voltage to the first sub-stage circuit, based on a third power source. The first sub-stage circuit includes: a first driver for controlling voltages of a first node and a second node, based on the input signal, the first clock signal, the second clock signal, the first power source, and the second power source; a second driver for controlling a voltage of an output node, based on the voltage of the first node, the voltage of the second node, the first power source, and the second power source; and an output unit for outputting the first scan signal through a first output terminal, based on the voltage of the output node, the first power source, and the second power source.
1. A scan driver comprising:
a plurality of stages configured to supply scan signals to scan lines,
wherein a first stage among the stages includes:
a first sub-stage circuit configured to generate a first scan signal, based on an input signal, a first clock signal, a second clock signal, a first power source, and a second power source; and
a first charge pump circuit configured to supply a bias voltage to the first sub-stage circuit, based on a third power source, and
wherein the first sub-stage circuit includes:
a first driver configured to control voltages of a first node and a second node, based on the input signal, the first clock signal, the second clock signal, the first power source, and the second power source;
a second driver configured to control a voltage of an output node, based on the voltage of the first node, the voltage of the second node, the first power source, and the second power source; and
an output unit configured to output the first scan signal through a first output terminal, based on the voltage of the output node, the first power source, and the second power source.
2. The scan driver of claim 1 , wherein the output unit includes an n-type transistor and a p-type transistor, and
wherein the first charge pump circuit supplies the bias voltage to a back-gate electrode of the n-type transistor included in the output unit.
3. The scan driver of claim 1 , wherein a voltage level of the third power source is lower than a voltage level of the first power source and is higher than a voltage level of the second power source, and
wherein a voltage level of the bias voltage is lower than the voltage level of the second power source.
4. The scan driver of claim 1 , wherein the first driver includes:
a first transistor connected between a first input terminal to which the input signal is supplied and an input node, the first transistor including a gate electrode connected to a second input terminal to which the first clock signal is supplied;
a second transistor including a first electrode connected to a first power input terminal to which a voltage of the first power source is supplied and a gate electrode connected to the second node;
a third transistor connected between a second electrode of the second transistor and the input node, the third transistor including a gate electrode connected to a third input terminal to which the second clock signal is supplied;
a fourth transistor connected between the second node and the second input terminal, the fourth transistor including a gate electrode connected to the input node;
a fifth transistor connected between the second node and a second power input terminal to which a voltage of the second power source is supplied, the fifth transistor including a gate electrode connected to the second input terminal; and
a sixth transistor connected between the input node and the first node, the sixth transistor including a gate electrode connected to the second power input terminal.
5. The scan driver of claim 4 , wherein the first driver further includes a first capacitor connected between the first power input terminal and the second node.
6. The scan driver of claim 1 , wherein the second driver includes:
a seventh transistor connected between a first power input terminal to which a voltage of the first power source is supplied and the output node, the seventh transistor including a gate electrode connected to the second node; and
an eighth transistor connected between the output node and a third input terminal to which the second clock signal is supplied, the eighth transistor including a gate electrode connected to the first node.
7. The scan driver of claim 6 , wherein the second driver further includes a second capacitor connected between the output node and the first node.
8. The scan driver of claim 1 , wherein the output unit includes:
a ninth transistor connected between a first power input terminal to which a voltage of the first power source is supplied and the first output terminal, the ninth transistor including a gate electrode connected to the output node; and
a tenth transistor connected between the first output terminal and a second power input terminal to which a voltage of the second power source is supplied, the tenth transistor including a gate electrode connected to the output node.
9. The scan driver of claim 8 , wherein the ninth transistor is a p-type transistor, and the tenth transistor is an n-type transistor.
10. The scan driver of claim 1 , wherein the first charge pump circuit includes:
an eleventh transistor connected between a third power input terminal to which a voltage of the third power source is supplied and a third node, the eleventh transistor including a gate electrode connected to the third power input terminal;
a twelfth transistor including a first electrode connected to a third input terminal to which the second clock signal is supplied and a gate electrode connected to the third node;
a third capacitor connected between a second electrode of the twelfth transistor and the third node;
a fourth capacitor including a first electrode connected to any one of a first power input terminal to which a voltage of the first power source is supplied, a second power input terminal to which a voltage of the second power source is supplied, and the third power input terminal; and
a thirteenth transistor connected between a second electrode of the fourth capacitor and the third node, the thirteenth transistor including a gate electrode connected to the third node.
11. The scan driver of claim 1 , wherein the first charge pump circuit includes:
a fourteenth transistor including a first electrode connected to a third power input terminal to which a voltage of the third power source is supplied and a gate electrode connected to a second input terminal to which the first clock signal is supplied;
an eleventh transistor connected between a second electrode of the fourteenth transistor and a third node, the eleventh transistor including a gate electrode connected to a second power input terminal to which a voltage of the second power source is supplied;
a twelfth transistor including a first electrode connected to a third input terminal to which the second clock signal is supplied and a gate electrode connected to the third node; and
a third capacitor connected between a second electrode of the twelfth transistor and the third node.
12. The scan driver of claim 11 , wherein the first charge pump circuit further includes:
a fourth capacitor including a first electrode connected to any one of a first power input terminal to which a voltage of the first power source is supplied, the second power input terminal, and the third power input terminal; and
a thirteenth transistor connected between a second electrode of the fourth capacitor and the third node, the thirteenth transistor including a gate electrode connected to the third node.
13. The scan driver of claim 12 , wherein the bias voltage corresponds to a voltage of a node to which the second electrode of the fourth capacitor is connected.
14. The scan driver of claim 11 , wherein the first charge pump circuit further includes:
a fourth capacitor including a first electrode connected to any one of a first power input terminal to which a voltage of the first power source is supplied, the second power input terminal, and the third power input terminal;
a thirteenth transistor including a first electrode connected to a second electrode of the fourth transistor, a second electrode, and a gate electrode; and
a fifteenth transistor connected between a node to which the second electrode and the gate electrode of the thirteenth transistor are connected and the third node, the fifteenth transistor including a gate electrode connected to the third node.
15. A scan driver comprising:
a plurality of sub-stage circuits configured to supply scan signals to scan lines and a plurality of charge pump circuits configured to generate a bias voltage,
wherein each of the sub-stage circuits includes:
a first driver configured to control voltages of a first node and a second node, based on an input signal, a first clock signal, a second clock signal, a first power source, and a second power source;
a second driver configured to control a voltage of an output node, based on the voltage of the first node, the voltage of the second node, the first power source, and the second power source; and
an output unit configured to output a scan signal through an output terminal, based on the voltage of the output node, the first power source, and the second power source, and
wherein a first sub-stage circuit configured to generate a first scan signal as the scan signal and a second sub-stage circuit configured to generate a second scan signal as the scan signal among the sub-stage circuits are commonly connected to a first charge pump circuit among the charge pump circuits.
16. The scan driver of claim 15 , wherein the first charge pump circuit supplies the bias voltage to each of the output unit included in the first sub-stage circuit and the output unit included in the second sub-stage circuit.
17. A scan driver comprising:
a plurality of stages configured to supply first sub-scan signals to first sub-scan lines, and supply second sub-scan signal to second sub-scan lines,
wherein a first stage among the stages includes:
a first sub-stage circuit configured to generate a (1-1)th sub-scan signal and a (2-1)th sub-scan signal, based on an input signal, a first clock signal, a second clock signal, a fourth clock signal, a first power source, and a second power source; and
a first charge pump circuit configured to supply a bias voltage to the first sub-stage circuit, based on a third power source,
wherein the first sub-stage circuit includes:
a first driver configured to control voltages of a first node and a second node, based on the input signal, the first clock signal, the second clock signal, the first power source, and the second power source;
a second driver configured to control a voltage of an output node, based on the voltage of the first node, the voltage of the second node, the first power source, and the fourth clock signal;
a first sub-output unit configured to output the (1-1)th sub-scan signal through a (1-1)th sub-output terminal, based on the voltage of the output node, the first power source, and the second power source; and
a second sub-output unit configured to output the (2-1)th sub-scan signal through a (2-1)th sub-output terminal, based on the voltage of the first node, the voltage of the second node, the first power source, and the second clock signal, and
wherein the (1-1)th sub-scan signal has a pulse of a high level, and the (2-1)th sub-scan signal has a pulse of a low level.
18. The scan driver of claim 17 , wherein the first sub-output unit includes:
a ninth transistor connected between a first power input terminal to which a voltage of the first power source is supplied and the (1-1)th sub-output terminal, the ninth transistor including a gate electrode connected to the output node; and
a tenth transistor connected between the (1-1)th sub-output terminal and a fifth input terminal to which the fourth clock signal is supplied, the tenth transistor including a gate electrode connected to the output node, and
wherein the ninth transistor is a p-type transistor, and the tenth transistor is an n-type transistor.
19. The scan driver of claim 18 , wherein the second sub-output unit includes:
a sixteenth transistor connected between the first power input terminal and the (2-1)th sub-output terminal, the sixteenth transistor including a gate electrode connected to the second node; and
a seventeenth transistor connected between a third input terminal to which the second clock signal is supplied and the (2-1)th sub-output terminal, the seventeenth transistor including a gate electrode connected to the first node.
20. The scan driver of claim 17 , wherein the first stage among the stages receives the fourth clock signal, and
a second stage among the stages receives a third clock signal, and
wherein the fourth clock signal is a signal shifted from the third clock signal.