IP Library Granted Patent US 11,907,538
Granted Patent B2
US 11,907,538 · App. 18/045,067 · Granted Feb 20, 2024

Extended utilization area for a memory device

Inventors: Jani Hyvonen (Tampere, FI); Kimmo J. Mylly (Ylojarvi, FI); Jussi Hakkinen (Tampere, FI); Yevgen Gyl (Tampere, FI)
Assignee: Memory Technologies LLC
G06F3/061G06F3/0659G06F3/0673G06F12/0646G06F12/1458G06F13/1694G06F13/28G11C7/20G06F12/1433G06F12/1441G06F21/79G06F2212/1052Y02D10/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,907,538
App. No.
18/045,067
Granted
Feb 20, 2024
Kind
B2
Abstract

Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Claims (44)

1. A memory device comprising:

a memory configured to be accessed according to a plurality of predefined access types, the plurality of predefined access types including at least a sequential access type; and

a controller configured to:

receive, from a host device, at least one first command to configure access to the memory device in accordance with the at least one of the plurality of predefined access types such that at least a portion of the memory is configured according to the at least one of the plurality of predefined access types for at least one usage;

receive, after the at least one first command, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device; and

receive, after the at least one second command, at least one third command to write data to the portion of the memory according to the activated at least one of the plurality of predefined access types.

2. The memory device of claim 1 , wherein the controller is further configured to:

receive at least one fourth command to read from the memory according to the activated at least one of the plurality of predefined access types.

3. The memory device of claim 1 , wherein the at least one second command is used to access the memory.

4. The memory device of claim 1 , wherein the at least one second command activates two or more of the plurality of predefined access types in parallel.

5. The memory device of claim 1 , wherein the plurality of predefined access types comprises a default access type.

6. The memory device of claim 5 , wherein the default access type is preselected.

7. The memory device of claim 1 , wherein the memory comprises NAND memory and the at least the portion of the memory comprises a block of the NAND memory.

8. The memory device of claim 1 , wherein the controller is further configured to:

conduct two or more simultaneous memory access operations.

9. The memory device of claim 1 , wherein the controller is further configured to:

receive at least one fourth command to designate the at least one of the plurality of predefined access types associated with the memory device.

10. The memory device of claim 1 , wherein the at least the portion of the memory comprises a partition of the memory.

11. The memory device of claim 1 , wherein the controller is further configured to:

receive at least one fourth command to configure access to the memory device in accordance with a second one of the plurality of predefined access types such that at least a second portion of the memory is configured according to the second one of the plurality of predefined access types for at least one usage; and

receive at least one fifth command to activate the second one of the plurality of predefined access types associated with the memory device.

12. The memory device of claim 1 , further comprising one or more registers storing at least one of: (i) an indication of the plurality of predefined access types, (ii) the at least one of the plurality of predefined access types, or (iii) an at least one currently active predefined access type.

13. A method comprising:

receiving, by a controller of a memory device and from a host device at a first time, at least one first command to configure access to the memory device in accordance with at least one of a plurality of predefined access types;

configuring, based at least in part on the at least one first command, at least a portion of a memory of the memory device according to the at least one of the plurality of predefined access types for at least one usage;

receiving, at a second time after the first time, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device;

activating, based at least in part on the at least one second command, the at least one of the plurality of predefined access types associated with the memory device;

receiving, after the at least one second command, at least one third command to write data to the portion of the memory device according to the activated at least one of the plurality of predefined access types; and

writing, based at least in part on the at least one third command, data to the portion of the memory according to the activated at least one of the plurality of predefined access types.

14. The method of claim 13 , wherein the memory comprises NAND memory and the at least the portion of the memory comprises a block of the NAND memory.

15. The method of claim 13 , wherein the at least one first command instructs configuring two or more of the plurality of predefined access types in parallel.

16. The method of claim 13 , further comprising:

receiving at least one fourth command to configure access to the memory device in accordance with a second one of the plurality of predefined access types such that at least a second portion of the memory is configured according to the second one of the plurality of predefined access types for at least one usage; and

receive at least one fifth command to activate the second one of the plurality of predefined access types associated with the memory device.

17. The method of claim 13 , wherein at least the portion of the memory comprises a partition of the memory.

18. A host device, comprising:

an interface to couple the host device to a memory device having a memory configured to be accessed according to a plurality of predefined access types; and

a controller configured with logic instructions to:

send at least one first command to configure access to the memory device in accordance with the at least one of the plurality of predefined access types such that at least a portion of the memory is configured according to the at least one of the plurality of predefined access types for at least one usage;

send, after the at least one first command, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device; and

send, after the at least one second command, at least one third command to write data to the portion of the memory according to the at least one of the plurality of predefined access types.

19. The host device of claim 18 , wherein the at least one second command activates two or more of the plurality of predefined access types in parallel.

20. The host device of claim 18 , wherein the controller is further configured with the logic instructions to:

read one or more registers of the memory device to determine an indication of the plurality of predefined access types.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2023
From: HYVONEN, JANI; MYLLY, KIMMO; HAKKINEN, JUSSI; GYL, YEVGEN
To: NOKIA CORPORATION
Reel/Frame 063110/0016 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2023
From: NOKIA CORPORATION
To: NOKIA INC.
Reel/Frame 063110/0046 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2023
From: NOKIA INC.
To: MEMORY TECHNOLOGIES LLC
Reel/Frame 063110/0147 →
Continuity (9)
Continuation 17410588 · Aug 24, 2021
Continuation 16825653 · Mar 20, 2020
Continuation 16598894 · Oct 10, 2019
Continuation 15181293 · Jun 13, 2016
Continuation 14732507 · Jun 5, 2015
Continuation 13951169 · Jul 25, 2013
Continuation 13645588 · Oct 5, 2012
Continuation 12039672 · Feb 28, 2008
Related Publication 20230068142A1 · Mar 2, 2023
Cited By (2)
US 12,417,022 US 12,511,076