Semiconductor memory device with mesh support structure
A semiconductor device includes a cell substrate including a cell array region and an extension region surrounding the cell array region, a mold structure including gate electrodes sequentially stacked on the cell substrate, channel structures disposed on the cell array region and intersecting the gate electrodes, a bit-line connected to at least some of the channel structures, a block isolation region cutting the mold structure, a source layer disposed between the cell substrate and the mold structure and connected to a side surface of each of the channel structures, and a support layer disposed between the source layer and the mold structure on upper surfaces of the cell substrate and the source layer. The support layer includes a support structure contacting the upper surface of the cell substrate. The support structure includes a peripheral portion surrounding the cell array region, and a mesh portion disposed on the extension region.
1 . A semiconductor memory device comprising:
a cell substrate including a cell array region and an extension region surrounding the cell array region;
a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate, wherein the plurality of gate electrodes are stacked in a stepwise manner on the extension region;
a plurality of channel structures disposed on the cell array region and extending in a vertical direction intersecting an upper surface of the cell substrate, wherein each of the plurality of channel structures intersects the plurality of gate electrodes;
a bit-line extending in a first direction intersecting the vertical direction, wherein the bit-line is connected to at least some of the plurality of channel structures;
a block isolation region extending in a second direction intersecting the vertical direction and the first direction, wherein the block isolation region cuts the mold structure;
a source layer disposed between the cell substrate and the mold structure, and connected to a side surface of each of the plurality of channel structures; and
a support layer disposed between the source layer and the mold structure, wherein the support layer extends along and on the upper surface of the cell substrate and an upper surface of the source layer,
wherein the support layer includes a support structure in contact with the upper surface of the cell substrate, and
the support structure includes:
a peripheral portion continuously extending so as to surround the cell array region in a plan view of the device; and
a mesh portion disposed on the extension region and having a mesh shape in the plan view of the device.
2 . The semiconductor memory device of claim 1 , wherein each of the plurality of channel structures includes:
a semiconductor pattern extending in the vertical direction and extending through the mold structure; and
an information storage film interposed between the semiconductor pattern and each of the plurality of gate electrodes,
wherein the source layer extends through the information storage film and is connected to a side surface of the semiconductor pattern.
3 . The semiconductor memory device of claim 2 , wherein the information storage film includes a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially stacked on the side surface of the semiconductor pattern.
4 . The semiconductor memory device of claim 1 , further comprising:
a source sacrificial layer between the cell substrate and the support layer,
wherein the source sacrificial layer is disposed at a level the same as a level at which the source layer is disposed, and
the source layer and the source sacrificial layer include different materials.
5 . The semiconductor memory device of claim 4 , wherein at least a portion of the support structure is interposed between the source layer and the source sacrificial layer.
6 . The semiconductor memory device of claim 4 , wherein the source layer is disposed on the cell array region, and
the source sacrificial layer is disposed on the extension region.
7 . The semiconductor memory device of claim 1 , wherein the extension region includes first and second regions,
the first region and the cell array region are arranged along the first direction, while the cell array region and the second region are arranged along the second direction,
the support structure includes:
a plurality of first extensions disposed on the first region, arranged side by side and extending in the second direction; and
a plurality of second extensions disposed on the second region, arranged side by side, and extending in the first direction, and
the plurality of first extensions and the plurality of second extensions intersect each other to form the mesh portion.
8 . The semiconductor memory device of claim 7 , wherein the plurality of first extensions include a first inner extension adjacent to the cell array region,
the plurality of second extensions include a second inner extension adjacent to the cell array region, and
the first inner extension and the second inner extension constitute the peripheral portion.
9 . The semiconductor memory device of claim 1 , further comprising:
a peripheral circuit substrate;
a peripheral circuit element disposed on the peripheral circuit substrate;
an interline insulating film covering the peripheral circuit element; and
a line structure formed in the interline insulating film,
wherein the cell substrate is stacked on the interline insulating film.
10 . The semiconductor memory device of claim 9 , wherein the mold structure and the peripheral circuit element are interposed between the cell substrate and the peripheral circuit substrate.
11 . A semiconductor memory device comprising:
a cell substrate including a cell array region and a first region, wherein the cell array region and the first region are arranged along a first direction;
a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate, wherein the plurality of gate electrodes are stacked in a stepwise manner along the first direction on the first region;
a plurality of channel structures disposed on the cell array region and extending in a vertical direction intersecting an upper surface of the cell substrate, wherein each of the plurality of channel structures intersects the plurality of gate electrodes;
a block isolation region extending in a second direction intersecting the first direction, wherein the block isolation region cuts the mold structure;
a source layer disposed between the cell substrate and the mold structure, and connected to a side surface of each of the plurality of channel structures; and
a support layer disposed between the source layer and the mold structure, and extending along and on the upper surface of the cell substrate and an upper surface of the source layer,
wherein the support layer includes a support structure in contact with the upper surface of the cell substrate, and
the support structure includes a plurality of first extensions disposed on the first region, arranged side by side, and extending in the second direction.
12 . The semiconductor memory device of claim 11 , wherein the cell substrate further includes a second region,
the cell array region and the second region are arranged along the second direction, and
the plurality of gate electrodes are stacked in a stepwise manner along the second direction on the second region.
13 . The semiconductor memory device of claim 12 , wherein the support structure further includes a plurality of second extensions disposed on the second region, arranged side by side, and extending in the first direction.
14 . The semiconductor memory device of claim 11 , further comprising:
a source sacrificial layer between the cell substrate and the support layer,
wherein the source sacrificial layer is disposed at a level the same as a level at which the source layer is disposed, and
the source layer and the source sacrificial layer include different materials.
15 . An electronic system comprising:
a main substrate;
a semiconductor memory device disposed on the main substrate; and
a controller disposed on the main substrate and electrically connected to the semiconductor memory device,
wherein the semiconductor memory device includes:
a cell substrate including a cell array region and an extension region surrounding the cell array region;
a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate, wherein the plurality of gate electrodes are stacked in a stepwise manner on the extension region;
a plurality of channel structures disposed on the cell array region and extending in a vertical direction intersecting an upper surface of the cell substrate, wherein each of the plurality of channel structures intersects the plurality of gate electrodes;
a source layer disposed between the cell array region of the cell substrate and the mold structure, and connected to a side surface of each of the plurality of channel structures; and
a support layer disposed between the source layer and the mold structure, wherein the support layer extends along and on the upper surface of the cell substrate and an upper surface of the source layer,
wherein the support layer includes a support structure in contact with the upper surface of the cell substrate,
at least a portion of the support structure continuously extends, and surrounds the cell array region, and
the support structure is formed in a mesh shape on the extension region in a plan view of the device.
16 . The electronic system of claim 15 , wherein the semiconductor memory device further includes:
a plurality of bit-lines, wherein each of the plurality of bit-lines extends in a first direction intersecting the vertical direction, and is connected to at least some of the plurality of channel structures; and
a plurality of block isolation regions, wherein each of the plurality of block isolation regions extend in a second direction intersecting the vertical direction and the first direction, and cuts the mold structure.