IP Library › Granted Patent US 12,408,564
Granted Patent B2
US 12,408,564 · App. 18/052,590 · Granted Sep 2, 2025

Process-induced forming of oxide RRAM

Inventors: Takashi Ando (Eastchester, NY); Soon-Cheon Seo (Glenmont, NY); Youngseok Kim (Upper Saddle River, NJ); Hiroyuki Miyazoe (White Plains, NY)
Assignee: International Business Machines Corporation
H10N70/023H10N70/24H10N70/826H10N70/841H10N70/8833
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Quick Facts
Patent No.
US 12,408,564
App. No.
18/052,590
Granted
Sep 2, 2025
Kind
B2
Abstract

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Claims (16)

1. A method of forming a semiconductor structure, the method comprising:

forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein;

forming an oxide layer on top of the bottom electrode;

forming a top electrode on top of the oxide layer;

forming an encapsulation layer to cover the oxide layer and the top electrode;

forming a first interlevel-dielectric (ILD) layer on top of the top electrode;

forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact;

forming a capping layer on top of the first metal layer; and

causing formation of one or more filaments in the oxide layer.

2. The method of claim 1 , wherein the oxide layer is a layer of hafnium-oxide (HfO), tantalum-oxide (TaO), titanium-oxide (TiO), or a combination thereof; the capping layer is formed through a plasma-enhanced-chemical-vapor-deposition (PECVD) process; and the one or more filaments are formed during the PECVD process.

3. The method of claim 2 , further comprising, before forming the top electrode, subjecting the oxide layer to a plasma environment that contains hydrogen, thereby causing the oxide layer to contain hydrogen with a concentration level that is less than 10 20 atoms/cm 3 and to have oxygen vacancies.

4. The method of claim 3 , wherein causing the formation of one or more filaments in the oxide layer comprises funneling free electrons to the oxide layer during the PECVD process and using the oxygen vacancies as precursors in forming the one or more filaments.

5. The method of claim 1 , wherein the capping layer is a layer of carbon-hydrogen containing silicon-nitride that is formed through a plasma-enhanced-chemical-vapor-deposition process.

6. The method of claim 1 , wherein the capping layer is formed in a plasma-enhanced-chemical-vapor-deposition process in an environment that contains precursors of at least silicon, nitrogen, carbon, and hydrogen.

7. The method of claim 1 , wherein the encapsulation layer is a conformal dielectric layer.

8. The method of claim 1 , wherein the via contact is made through the encapsulation layer to be in direct contact with the top electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2022
From: ANDO, TAKASHI; SEO, SOON-CHEON; KIM, YOUNGSEOK; MIYAZOE, HIROYUKI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 061653/0360 →
Continuity (1)
Related Publication 20240155952A1 · May 9, 2024
References Cited (14)
US 9362497B2 · Kumar · 2016 [cited by applicant]
US 9431609B2 · Dang · 2016 [cited by applicant]
US 10340451B2 · Tada · 2019 [cited by applicant]
US 10756266B2 · Wang · 2020 [cited by applicant]
US 11017852B2 · Tu · 2021 [cited by examiner]
US 11223008B2 · Rizzolo · 2022 [cited by examiner]
US 11844290B2 · Koty et al. · 2023 [cited by applicant]
US 20210234096A1 · Consiglio · 2021 [cited by applicant]
US 20210336135A1 · Jiang · 2021 [cited by applicant]
Radamson et al., “Miniaturization of CMOS”, Micromachines 2019, 10, 293, pp. 1-52. [cited by applicant]
Su et al., “A Method to Reduce Forming Voltage Without Degrading Device Performance in Hafnium Oxide-Based 1T1R Resistive Random Access Memory”, Journal of the Electron Devices Society, vol. 6, Date of publication Feb. … [cited by applicant]
Waser, “EMRL Electronic Materials Research Laboratory”, http://www.emrl.de/r_a_1.htm, Accessed on Aug. 24, 2022, 10 pages. [cited by applicant]
Wong et al., “Metal-Oxide RRAM”, Invited Paper, Proceedings of the IEEE, vol. 100, No. 6, Jun. 2012, pp. 1951-1970. [cited by applicant]
Wu et al., “Fundamental limitations of existing models and future solutions for dielectric reliability and RRAM applications (Invited)”, © 2017 IEEE, IEDM17, pp. 21.5.1-21.5.4. [cited by applicant]