Resistive random-access memory with protected switching layer
Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer.
1. A resistive random-access memory (RRAM) device comprising:
an intermediate first layer that includes a switching region with added switching species of at least one different material;
a device layer of a semiconductor material at one side of the intermediate layer and includes a first doped region, and a substrate layer of a semiconductor material at an opposite side of the first layer and comprises a second doped region;
electrodes that are spaced from said switching region and contact said first and second doped regions; and
wherein said switching region is configured to switch between higher and lower resistivity states in response to a switching voltage without having been conditioned with a higher, breakdown voltage.
2. The RRAM device of claim 1 , further including one or more active electronic circuits formed in one or both of said device and substrate layers.
3. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said device layer.
4. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said substrate layer.
5. The RRAM device of claim 2 , in which at least one of said electrodes has a contact that extends through said device layer and said intermediate layer to said second doped region but is spaced from said switching region.
6. The RRAM device of claim 2 , in which said intermediate layer and said device and substrate layers comprise a single chip and said switching region and first and second doped regions are configured as plural, individually addressed resistive memory elements.
7. The RRAM device of claim 6 , in which said resistive memory elements are characterized by a lifetime of 100 million or more switching cycles.
8. The RRAM device of claim 6 , in which said resistive memory elements are characterized by differences of less than 10 percent in their respective switching voltages.
9. The RRAM device of claim 6 , wherein said electrodes are configured to couple selected ones of said individually addressable resistive memory elements with respective ones of said one or more active electronic circuits.
10. The RRAM device of claim 6 , in which said one or more active electronic circuits comprise at least one first circuit that is surrounded by said individually addressable resistive memory elements.
11. The RRAM device of claim 10 , in which said one or more active electronic circuits further comprise at least one second circuit that is not surrounded by said individually addressable resistive memory devices.
12. A resistive random-access memory (RRAM) device comprising:
a first layer comprising a switching region with added switching species of at least one different material;
a device layer of Si with a first doped region at one side of the switching region, and a substrate layer of Si with a second doped region at an opposite side of the switching region; and
electrodes that are spaced from said switching region and contact said first and second doped regions;
wherein said switching region is configured to switch between higher and lower resistivity states in response to a switching voltage absent prior conditioning with a higher, breakdown voltage.
13. The RRAM device of claim 12 , in which said first layer is a buried oxide layer (BOX) and said switching region comprises a portion thereof that has said added switching species of at least one different material.
14. The RRAM device of claim 12 , in which said first and second doped regions are offset relative to each other but each has a portion coextensive with said switching region.
15. The RRAM device of claim 14 , in which said electrodes contact portions of said doped regions that are not coextensive with said switching region.
16. The RRAM device of claim 12 , in which said first layer and said device and substrate layers are formed as a single chip and said switching region and first and second doped regions are configured as plural, individually addressed resistive memory elements.
17. The RRAM device of claim 16 , further including at least one active electronic circuit formed in or on said single chip and interacting with said memory elements.
18. The RRAM device of claim 17 , in which said at least one active electronic circuit and said electrodes are at the same side of said switching region.
19. The RRAM device of claim 17 , in which said at least one active electronic circuit and said electrodes are at opposite sides of said switching region.
20. The RRAM device of claim 17 , in which said at least one active electronic circuit comprises at least one active electronic circuit that is surrounded by said memory elements.