IP Library › Granted Patent US 12,490,472
Granted Patent B2
US 12,490,472 · App. 18/052,957 · Granted Dec 2, 2025

Semiconductor device and semiconductor memory device

Inventors: Ha Hoang (Mie, JP); Kazuhiro Matsuo (Mie, JP); Kenichiro Toratani (Mie, JP)
Assignee: Kioxia Corporation
H10D30/6755H10D30/6757
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Quick Facts
Patent No.
US 12,490,472
App. No.
18/052,957
Granted
Dec 2, 2025
Kind
B2
Abstract

In general, according to one embodiment, a semiconductor device includes first to third conductors, a semiconductor, a first insulator, and an insulation region. The semiconductor includes a metal oxide and extends in the first direction to be in contact with the first conductor and the third conductor. The insulation region is surrounded by the semiconductor and extends in the first direction to be in contact with the first conductor. The semiconductor includes a first portion and a second portion defined between the first portion and the insulation region. A concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.

Claims (33)

1 . A semiconductor memory device comprising:

a cell capacitor and a transistor,

wherein the cell capacitor includes a first electrode coupled to a plate line and a second electrode coupled to the transistor, the transistor includes a first conductor, a second conductor, and a third conductor, which are aligned in a first direction and separated from each other;

a semiconductor including a metal oxide and extending in the first direction to be in contact with the first conductor and the third conductor;

a first insulator arranged between the semiconductor and the second conductor; and

an insulation region surrounded by the semiconductor and extending in the first direction to be in contact with the first conductor,

wherein the semiconductor includes a first portion and a second portion defined between the first portion and the insulation region, and

a concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.

2 . The semiconductor memory device according to claim 1 , wherein

the second conductor is arranged between the first conductor and the third conductor.

3 . The semiconductor memory device according to claim 1 , wherein

the second conductor surrounds the semiconductor.

4 . The semiconductor memory device according to claim 1 , wherein

the insulation region is in contact with the semiconductor.

5 . The semiconductor memory device according to claim 1 , wherein

the first element is a metallic element and has an oxygen-bonding energy that is largest among metallic elements included in the metal oxide.

6 . The semiconductor memory device according to claim 1 , wherein

the first element is gallium or aluminum.

7 . The semiconductor memory device according to claim 1 , wherein

the first element has an oxygen-bonding energy that is largest among elements included in the semiconductor.

8 . The semiconductor memory device according to claim 1 , wherein

the first element is carbon, hafnium, or silicon.

9 . The semiconductor memory device according to claim 1 , wherein

the insulation region includes a silicon oxide.

10 . The semiconductor memory device according to claim 1 , wherein

the insulation region is a void.

11 . The semiconductor memory device according to claim 1 , wherein

part of the semiconductor is arranged between the insulation region and the third conductor.

12 . The semiconductor memory device according to claim 1 , wherein

the insulation region is in contact with the third conductor.

13 . The semiconductor memory device according to claim 1 , wherein the second electrode of the cell capacitor is electrically coupled to the first conductor or the third conductor.

14 . The semiconductor memory device according to claim 1 , wherein

the first insulator is a gate insulating film of the transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2022
From: HOANG, HA; MATSUO, KAZUHIRO; TORATANI, KENICHIRO
To: KIOXIA CORPORATION
Reel/Frame 061669/0901 →
Priority Claims (1)
JP 2022-094570 · Jun 10, 2022 · national
Continuity (1)
Related Publication 20230402548A1 · Dec 14, 2023
References Cited (10)
US 9324880B2 · Ono et al. · 2016 [cited by applicant]
US 9478668B2 · Takahashi et al. · 2016 [cited by applicant]
US 10381220B2 · Benwadih et al. · 2019 [cited by applicant]
US 10439068B2 · Shimomura et al. · 2019 [cited by applicant]
US 20090294844A1 · Tanaka · 2009 [cited by examiner]
US 20160079268A1 · Sakuma · 2016 [cited by examiner]
US 20180025905A1 · Yamazaki et al. · 2018 [cited by applicant]
US 20180323311A1 · Zhai · 2018 [cited by applicant]
US 20220068967A1 · Yamazaki · 2022 [cited by examiner]
US 20220139917A1 · Yamazaki et al. · 2022 [cited by applicant]