IP Library › Granted Patent US 12,063,770
Granted Patent B2
US 12,063,770 · App. 17/414,614 · Granted Aug 13, 2024

Memory device and semiconductor device including the memory device

Inventors: Shunpei Yamazaki (Tokyo, JP); Kiyoshi Kato (Kanagawa, JP); Tatsuya Onuki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10B12/30H01L29/7869
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,063,770
App. No.
17/414,614
Granted
Aug 13, 2024
Kind
B2
Abstract

A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

Claims (49)

1. A memory device comprising a transistor and a capacitor,

wherein the transistor comprises:

a first oxide semiconductor;

a first conductor and a second conductor provided over a top surface of the first oxide semiconductor;

a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor;

a first insulator provided in contact with the second oxide semiconductor; and

a third conductor provided in contact with the first insulator,

wherein the capacitor comprises:

the second conductor;

a second insulator over the second conductor; and

a fourth conductor over the second insulator,

wherein the first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor, and

wherein a bottom surface of the second oxide semiconductor is in contact with a surface of the groove of the first oxide semiconductor.

2. The memory device according to claim 1 ,

wherein the first oxide semiconductor and the second oxide semiconductor each contain indium, an element M, and zinc, and

wherein the element M is gallium, yttrium, or tin.

3. The memory device according to claim 1 ,

wherein the first oxide semiconductor comprises a region having a higher atomic ratio of the indium than the second oxide semiconductor.

4. The memory device according to claim 1 ,

wherein the first oxide semiconductor and the second oxide semiconductor each have crystallinity.

5. A semiconductor device comprising:

the memory device according to claim 1 ; and

a device containing silicon,

wherein the memory device and the device containing silicon are electrically connected to each other.

6. A semiconductor device comprising the memory device according to claim 1 ,

wherein the memory device is a first memory device,

wherein the semiconductor device comprises:

the first memory device;

an n-th memory device over the first memory device; and

a device containing silicon which is electrically connected to the first memory device and the n-th memory device,

wherein the device containing silicon, the first memory device, and the n-th memory device are stacked in this order, and

wherein n is a natural number of 2 or more.

7. The semiconductor device according to claim 6 ,

wherein the n-th memory device comprises an oxide semiconductor.

8. A memory device comprising a transistor and a capacitor,

wherein the transistor comprises:

a first oxide semiconductor;

a first conductor and a second conductor provided over a top surface of the first oxide semiconductor;

a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor;

a first insulator provided in contact with the second oxide semiconductor; and

a third conductor provided in contact with the first insulator,

wherein the capacitor comprises:

the second conductor;

a second insulator over the second conductor; and

a fourth conductor over the second insulator,

wherein the first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor,

wherein the second oxide semiconductor, the first insulator, and the third conductor are embedded in the groove,

wherein the second oxide semiconductor has a curvature, and

wherein a bottom surface of the second oxide semiconductor is in contact with a surface of the groove of the first oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2021
From: YAMAZAKI, SHUNPEI; KATO, KIYOSHI; ONUKI, TATSUYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 056565/0914 →
Priority Claims (1)
JP 2018-248460 · Dec 28, 2018 · national
Continuity (1)
Related Publication 20220139917A1 · May 5, 2022