Semiconductor device structure including a bonding structure
A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
1. A semiconductor device structure, comprising:
a substrate;
a dielectric structure disposed on the substrate;
a pad embedded in the dielectric structure;
a conductive structure disposed on and coupled with an upper surface of the pad;
a buffer structure disposed on and coupled with an upper surface of the pad and separates the conductive structure from the dielectric structure, wherein the buffer structure is surrounded by the dielectric structure and sandwiched between the dielectric structure and the conductive structure, wherein a coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
2. The semiconductor device structure of claim 1 , further comprising a transistor electrically connected to the conductive structure.
3. The semiconductor device structure of claim 2 , further comprising a first connection feature electrically connecting the transistor and the pad, wherein a lateral surface of the first connection feature is free from covering of the buffer structure, and a second connection feature electrically connecting the pad and the first connection feature, and a lateral surface of the second connection feature is free from covering of the buffer structure, wherein the second connection feature comprises a via.
4. The semiconductor device structure of claim 1 , wherein the buffer structure comprises a polymer.
5. The semiconductor device structure of claim 1 , wherein the buffer structure comprises a developable material.
6. The semiconductor device structure of claim 1 , wherein the buffer structure is in physical contact with the conductive structure.
7. The semiconductor device structure of claim 1 , wherein the buffer structure is in physical contact with the dielectric structure.
8. The semiconductor device structure of claim 1 , wherein a first portion of the pad is in contact with the buffer structure, and a second portion of the pad is in contact with conductive structure.
9. The semiconductor device structure of claim 8 , wherein a third portion of the pad is in contact with the dielectric structure.
10. The semiconductor device structure of claim 1 , wherein a height of the buffer structure is substantially the same as a height of the conductive structure.
11. A semiconductor device structure, comprising:
a substrate;
a first conductive layer disposed on the substrate and located at a first level;
a second conductive layer disposed on the substrate and located at a second level higher than the first level;
a dielectric structure disposed covering the first conductive layer and the second conductive layer; and
a buffer structure separating the first conductive layer and the dielectric structure; wherein the buffer structure is located at the first level, and the buffer structure is surrounded by the dielectric structure and sandwiched between the dielectric structure and the conductive structure.
12. The semiconductor device structure of claim 11 , wherein a lateral surface of the second conductive layer is free from covering of the buffer structure.
13. The semiconductor device structure of claim 11 , further comprising:
a third conductive layer disposed on the substrate and located at a third level lower than the first level, and a lateral surface of the third conductive layer is free from covering of the buffer structure;
a dummy buffer structure located at the first level;
a dummy pad on which the dummy buffer structure is disposed;
a circuit layer disposed over the second conductive layer, wherein the dummy pad is electrically isolated from the circuit layer; and
a transistor electrically connected to the first conductive layer.
14. The semiconductor device structure of claim 13 , further comprising a first connection feature electrically connecting the transistor and the third conductive layer, wherein a lateral surface of the first connection feature is free from covering of the buffer structure, and a second connection feature electrically connecting the third conductive layer and the first connection feature, and a lateral surface of the second connection feature is free from covering of the buffer structure.
15. The semiconductor device structure of claim 11 , wherein the buffer structure is in physical contact with the first conductive layer, and the buffer structure is in physical contact with the dielectric structure.
16. The semiconductor device structure of claim 13 , wherein a first portion of the third conductive layer is in contact with the buffer structure, and a second portion of the third conductive layer is in contact with first conductive layer.
17. A method of manufacturing a semiconductor device structure, comprising:
providing a first carrier, wherein the first carrier comprises a first dielectric structure and a first conductive layer exposed by the dielectric structure;
forming a buffer structure on an upper surface of the first conductive layer and within an opening of the dielectric structure, wherein the buffer structure is surrounded by the dielectric structure;
forming a first bonding pad on the upper surface of the first conductive layer, and wherein the first bonding pad is separated from the first dielectric structure by the buffer structure, wherein the buffer structure is sandwiched between the dielectric structure and the conductive structure; and
bonding the first carrier and a second carrier through the first bonding pad.
18. The method of claim 17 , wherein the second carrier comprises a second bonding pad and a second buffer structure, and bonding the first carrier and the second carrier comprises:
bonding the second bonding pad to the first bonding pad; and
bonding a second buffer layer of the second carrier to a first buffer layer of the first carrier.
19. The method of claim 17 , wherein a CTE of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the first bonding pad, the buffer structure comprises a polymer.
20. The method of claim 17 , wherein the first carrier comprises a test pad exposed by the dielectric structure, and the method further comprises:
forming a buffer layer covering the test pad.