Package including multiple semiconductor devices
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
1. An apparatus, comprising:
a package including:
a common gate conductor,
a first semiconductor die having a die gate conductor, and
a second semiconductor die having a die gate conductor;
a first conductive path, including a first wirebond, between the common gate conductor and the die gate conductor of the first semiconductor die; and
a second conductive path, including a second wirebond, between the common gate conductor and the die gate conductor of the second semiconductor die.
2. The apparatus of claim 1 , wherein the first conductive path has a length substantially equal to a length of the second conductive path.
3. The apparatus of claim 1 , further comprising:
a third wirebond between the first semiconductor die and the second semiconductor die.
4. The apparatus of claim 3 , further comprising:
a substrate, the common gate conductor being included in the substrate; and
a fourth wirebond between the second semiconductor die and the substrate.
5. The apparatus of claim 1 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane and are electrically coupled to a leadframe, the common gate conductor being included in the leadframe.
6. The apparatus of claim 1 , wherein the die gate conductor of the first semiconductor die is oriented with respect to the common gate conductor so that a length of the first conductive path is minimized.
7. The apparatus of claim 1 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane, the first semiconductor die having an edge parallel to an edge of the second semiconductor die.
8. The apparatus of claim 1 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane, the first semiconductor die having an edge non-parallel to an edge of the second semiconductor die.
9. The apparatus of claim 1 , further comprising:
a plurality of semiconductor die including the first semiconductor die, the second semiconductor die, and a third semiconductor die having a die gate conductor,
the common gate conductor being centered between the die gate conductors of the plurality of semiconductor die.
10. The apparatus of claim 1 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane,
the apparatus further comprising:
a diode aligned along the same plane, the first semiconductor die and the second semiconductor die being disposed between the diode and the common gate conductor.
11. An apparatus, comprising:
a first package including a gate metal runner;
a second package disposed in the first package and including:
a first silicon carbide die having a gate conductor, and
a second silicon carbide die having a gate conductor;
a first conductive path, including a first wirebond, between the gate metal runner and the gate conductor of the first silicon carbide die; and
a second conductive path, including a second wirebond, between the gate metal runner and the gate conductor of the second silicon carbide die.
12. The apparatus of claim 11 , wherein the first conductive path has a length substantially equal to a length of the second conductive path.
13. The apparatus of claim 11 , further comprising:
a third wirebond between the first silicon carbide die and the second silicon carbide die.
14. The apparatus of claim 13 , further comprising:
a substrate, the gate conductor being included in the substrate; and
a fourth wirebond between the second silicon carbide die and the substrate.
15. The apparatus of claim 11 , wherein the first silicon carbide die and the second silicon carbide die are aligned along a same plane and are electrically coupled to a leadframe, the gate metal runner being electrically coupled to the leadframe.
16. The apparatus of claim 11 , wherein the gate conductor of the first silicon carbide die is oriented with respect to the gate metal runner so that a length of the first conductive path is minimized.
17. The apparatus of claim 11 , wherein the first silicon carbide die and the second silicon carbide die are aligned along a same plane, the first silicon carbide die having an edge parallel to an edge of the second silicon carbide die.
18. The apparatus of claim 11 , wherein the first silicon carbide die and the second silicon carbide die are aligned along a same plane, the first silicon carbide die having an edge non-parallel to and non-orthogonal to an edge of the second silicon carbide die.
19. The apparatus of claim 11 , further comprising:
a plurality of silicon carbide die including the first silicon carbide die, the second silicon carbide die, and a third silicon carbide die having a gate conductor,
a leadframe, the first silicon carbide die, the second silicon carbide die, and the third silicon carbide die are electrically coupled to a leadframe, the gate metal runner being electrically coupled to the leadframe using a via,
the via being centered between the die gate conductors of the plurality of silicon carbide die.
20. The apparatus of claim 11 , wherein the first silicon carbide die and the second silicon carbide die are aligned along a same plane,
the apparatus further comprising:
a diode aligned along the same plane, the first silicon carbide die and the second silicon carbide die being disposed between the diode and the gate conductor.