Vertical semiconductor devices
A vertical semiconductor device includes insulation patterns, channel structures, a first metal pattern structure and a second metal pattern. The insulation patterns are spaced apart from each other in a vertical direction. Each insulation pattern extends in a first direction parallel to the upper surface of a substrate. The channel structures pass through the insulation patterns. The first metal pattern structure include at least one first metal material, and extend in the first direction. The first metal pattern structure are positioned in a gap between adjacent insulation patterns in the vertical direction, and the first metal pattern structure is at a central portion of the gap. The second metal pattern includes a metal material that is different from the at least one first metal material, the second metal pattern may be on opposite sidewalls of the first metal pattern structure to fill a remainder portion of the gap.
1 . A vertical semiconductor device, comprising:
insulation patterns that are spaced apart from each other in a vertical direction perpendicular to an upper surface of a substrate, each of the insulation patterns extending in a first direction parallel to the upper surface of the substrate;
channel structures on the substrate, the channel structures passing through the insulation patterns, the channel structures including first channel structures and second channel structures;
a first metal pattern structure including at least one first metal material, and comprising a continuous portion of the first metal pattern structure having an elongated shape extending in the first direction, wherein the first metal pattern structure is located between adjacent insulation patterns of the insulation patterns in the vertical direction; and
a second metal pattern including a metal material that is different from the at least one first metal material, the second metal pattern on opposite outer sidewalls of the elongated shape of the continuous portion of the first metal pattern structure in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate,
such that the continuous portion of the first metal pattern structure is between and in contact with separate portions of the second metal pattern in the second direction,
wherein the first metal pattern structure contacts only the first channel structures among the first channel structures and the second channel structures,
wherein, in a cross-sectional view of the first metal pattern structure and the second metal pattern taken along the second direction:
a third channel structure, a fourth channel structure, and a fifth channel structure of the channel structures are arranged in sequence,
the second metal pattern is between the third channel structure and the fourth channel structure, and between the fourth channel structure and the fifth channel structure, and
the first metal pattern structure is present between the fourth channel structure and the fifth channel structure and absent between the third channel structure and the fourth channel structure.
2 . The vertical semiconductor device of claim 1 ,
wherein the first metal pattern structure includes a first barrier metal pattern and a first metal pattern, and
wherein the first barrier metal pattern is between the first channel structures and the first metal pattern in the first direction.
3 . The vertical semiconductor device of claim 2 ,
wherein the first barrier metal pattern includes titanium, titanium nitride, tantalum, or tantalum nitride, and
wherein the first metal pattern includes tungsten, cobalt, molybdenum, or ruthenium.
4 . The vertical semiconductor device of claim 1 ,
wherein the first metal pattern structure includes only a barrier metal pattern, and
wherein the barrier metal pattern includes titanium, titanium nitride, tantalum, or tantalum nitride.
5 . The vertical semiconductor device of claim 1 , wherein the first metal pattern structure includes tungsten, and the second metal pattern includes molybdenum.
6 . The vertical semiconductor device of claim 1 , further comprising a blocking dielectric layer conformally on surfaces of the insulation patterns and sidewalls of the channel structures, and
wherein upper and lower surfaces of the second metal pattern are in contact with the blocking dielectric layer.
7 . The vertical semiconductor device of claim 1 , wherein the first metal pattern structure is arranged centrally between a pair of second insulation patterns spaced apart from each other in the second direction, and
wherein a length in the second direction of the first metal pattern structure is greater than 2 nm and is less than 40% of a distance in the second direction between the pair of second insulation patterns.
8 . The vertical semiconductor device of claim 1 , wherein a maximum grain size of the second metal pattern is a same magnitude as a magnitude of a vertical height of the second metal pattern.
9 . The vertical semiconductor device of claim 1 , wherein the second metal pattern has an electrical resistance lower than an electrical resistance of the first metal pattern structure.
10 . A vertical semiconductor device, comprising:
first insulation patterns that are spaced apart from each other in a vertical direction perpendicular to an upper surface of a substrate, each of the first insulation patterns extending in a first direction parallel to the upper surface of the substrate;
a pair of second insulation patterns spaced apart from each other in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate, wherein the second insulation patterns extend in the first direction;
channel structures on the substrate, the channel structures passing through the first insulation patterns between the pair of second insulation patterns, the channel structures including first channel structures and second channel structures;
a blocking dielectric layer conformally on surfaces of the first insulation patterns and sidewalls of the channel structures between adjacent first insulation patterns of the first insulation patterns in the vertical direction;
a first metal pattern structure including a first barrier metal pattern and a first metal pattern, the first metal pattern structure extending in the first direction parallel to the second insulation patterns and having a linear shape extending in the first direction in a plan view; and
a second metal pattern on each of opposite outer sidewalls of the linear shape of the first metal pattern structure in the second direction,
wherein the first metal pattern structure contacts only the first channel structures among the first channel structures and the second channel structures,
wherein the first metal pattern structure is centrally between the pair of second insulation patterns and the second metal pattern at least partially fills a remainder portion of a space between the pair of second insulation patterns on opposite outer sides of the linear shape of the first metal pattern structure in the second direction, such that the second metal pattern is between the opposite outer sidewalls of the linear shape of the first metal pattern structure and the pair of second insulation patterns, and such that the first metal pattern structure is between separate portions of the second metal pattern in the second direction, and
wherein one sidewall of the second metal pattern is in contact with the first metal pattern structure, and upper and lower surfaces of the second metal pattern are in contact with the blocking dielectric layer, respectively,
wherein, in a cross-sectional view of the first metal pattern structure and the second metal pattern taken along the second direction:
a third channel structure, a fourth channel structure, and a fifth channel structure of the channel structures are arranged in sequence,
the second metal pattern is between the third channel structure and the fourth channel structure, and between the fourth channel structure and the fifth channel structure, and
the first metal pattern structure is present between the fourth channel structure and the fifth channel structure and absent between the third channel structure and the fourth second channel structure.
11 . The vertical semiconductor device of claim 10 ,
wherein the first barrier metal pattern includes titanium, titanium nitride, tantalum, or tantalum nitride, and
wherein the first metal pattern includes tungsten, cobalt, molybdenum, or ruthenium.
12 . The vertical semiconductor device of claim 10 , wherein the second metal pattern includes tungsten, cobalt, molybdenum, or ruthenium.
13 . The vertical semiconductor device of claim 10 ,
wherein the first metal pattern includes tungsten, and
wherein the second metal pattern includes molybdenum.
14 . The vertical semiconductor device of claim 10 , wherein a maximum grain size of the second metal pattern is a same magnitude as a magnitude of a vertical height of the second metal pattern.
15 . The vertical semiconductor device of claim 10 , wherein the second metal pattern has an electrical resistance lower than an electrical resistance of the first metal pattern structure.
16 . A vertical semiconductor device, comprising:
a lower circuit pattern on a substrate;
a common electrode plate on the lower circuit pattern;
insulation patterns on the common electrode plate, the insulation patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the insulation patterns extending in a first direction parallel to the upper surface of the substrate;
channel structures connected to the common electrode plate through the insulation patterns, each of the channel structures including a channel extending in the vertical direction, and
a charge storage structure surrounding an outer wall of the channel;
a blocking dielectric layer conformally on surfaces of the insulation patterns and sidewalls of the channel structures between adjacent insulation patterns of the insulation patterns in the vertical direction;
a first metal pattern structure including at least one first metal material and extending in the first direction, wherein the first metal pattern structure is between the adjacent insulation patterns in the vertical direction; and
a second metal pattern including a metal material different from the at least one first metal material, wherein the second metal pattern is on opposing second sidewalls of the first metal pattern structure in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate,
wherein one sidewall of the second metal pattern is in contact with the first metal pattern structure, and upper and lower surfaces of the second metal pattern are in contact with the blocking dielectric layer, respectively, and
wherein, in a plan view, one or more first channel structures of the channel structures are completely surrounded by only the second metal pattern from among the first metal pattern structure and the second metal pattern,
wherein, in a cross-sectional view of the first metal pattern structure and the second metal pattern taken along the second direction:
a third channel structure, a fourth channel structure, and a fifth channel structure of the channel structures are arranged in sequence,
the second metal pattern is between the third channel structure and the fourth channel structure, and between the fourth channel structure and the fifth channel structure, and
the first metal pattern structure is present between the fourth channel structure and the fifth channel structure and absent between the third channel structure and the fourth second channel structure.
17 . The vertical semiconductor device of claim 16 , wherein, in the plan view, one or more second channel structures of the channel structures are surrounded collectively by the first metal pattern structure and the second metal pattern.