IP Library › Granted Patent US 9,859,294
Granted Patent B2
US 9,859,294 · App. 15/679,613 · Granted Jan 2, 2018

Semiconductor device and manufacturing method thereof

Inventor: Kwang Hee Han (Chungcheongbuk-do, KR)
Assignee: SK Hynix Inc.
H01L27/11565H01L21/76816H01L21/76877H01L23/528H01L23/5226H01L23/53257H01L27/11568H01L27/11582
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Quick Facts
Patent No.
US 9,859,294
App. No.
15/679,613
Granted
Jan 2, 2018
Kind
B2
Abstract

A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers surrounding sidewalls of the channel layers; stacked gate electrodes interposed between the insulating layers, the gate electrodes respectively surrounding the channel layers; and stacked gate lines interposed between the insulating layers, the gate lines electrically connecting the gate electrodes to each other.

Claims (20)

1. A method of manufacturing a semiconductor device, the method comprising:

alternately forming sacrificial layers and insulating layers;

forming first openings passing through the sacrificial layers and the insulating layers, the first openings being arranged in a first direction and a second direction intersecting the first direction;

forming second openings by partially removing the sacrificial layers exposed through the first openings;

forming gate electrodes in the second openings;

forming channel layers in the first openings;

forming a slit passing through the sacrificial layers and the insulating layers;

forming third openings by removing the sacrificial layers through the slit; and

forming, in the third openings, gate lines electrically connecting the gate electrodes to each other.

2. The method of claim 1 , wherein the gate electrodes and the gate lines include a metal.

3. The method of claim 1 , wherein the forming of the gate electrodes includes:

forming a metal layer in the first openings and the second openings; and

forming metal patterns in the respective second openings by removing the metal layer formed in the first openings.

4. The method of claim 3 , further comprising:

forming fourth openings by partially removing the metal patterns through the first openings; and

forming barrier patterns in the fourth openings.

5. The method of claim 1 , further comprising forming memory layers in the first openings, before the channel layers are formed.

6. The method of claim 1 , wherein a first distance between neighboring first openings in the first direction is wider than a second distance between neighboring first openings in the second direction.

7. The method of claim 6 , wherein a sum of widths of neighboring second openings in the first direction is smaller than the first distance, and a sum of widths of neighboring second openings in the second direction is substantially equal to or greater than the second distance.

8. The method of claim 1 , wherein the neighboring second openings in the first direction are isolated from each other, and the neighboring second openings in the second direction are directly connected to each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2017
From: HAN, KWANG HEE
To: SK HYNIX INC.
Reel/Frame 043585/0759 →
Priority Claims (1)
KR 10-2015-0182898 · Dec 21, 2015 · national
Continuity (2)
Continuation 15150249 · May 9, 2016
Related Publication 20170345839A1 · Nov 30, 2017