Three-dimensional non-volatile memory device including horizontal channel region
A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.
1 . A three-dimensional non-volatile memory device comprising:
a memory cell array comprising
a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate, the first lateral direction and the second lateral direction being parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction being perpendicular to the main surface of the substrate,
a plurality of horizontal channel regions extending in the first lateral direction on the substrate, the plurality of horizontal channel regions overlapping each other and apart from each other in the vertical direction,
a vertical word line passing through the plurality of horizontal channel regions in the vertical direction, and
a ferroelectric layer between the vertical word line and the plurality of horizontal channel regions, the ferroelectric layer passing through the plurality of horizontal channel regions in the vertical direction.
2 . The three-dimensional non-volatile memory device of claim 1 , wherein
the memory cell array further comprises a plurality of inter-cell insulation patterns respectively one by one between the plurality of horizontal channel regions, the plurality of inter-cell insulation patterns overlapping the plurality of horizontal channel regions in the vertical direction, and
the vertical word line comprises
a plurality of first local regions surrounded by the plurality of horizontal channel regions, and
a plurality of second local regions surrounded by the plurality of inter-cell insulation patterns.
3 . The three-dimensional non-volatile memory device of claim 1 , wherein the memory cell array further comprises:
a plurality of interface dielectric layers between the ferroelectric layer and the plurality of horizontal channel regions, the plurality of interface dielectric layers being at the same vertical level as the plurality of horizontal channel regions, wherein
the ferroelectric layer surrounds an outer surface of the vertical word line and is in contact with the outer surface of the vertical word line.
4 . The three-dimensional non-volatile memory device of claim 1 , wherein the memory cell array further comprises:
a plurality of interface dielectric layers between the vertical word line and the plurality of horizontal channel regions, the plurality of interface dielectric layers being at the same vertical level as the plurality of horizontal channel regions; and
a plurality of metal-containing patterns between the vertical word line and the plurality of interface dielectric layers, the plurality of metal-containing patterns being at the same vertical level as the plurality of horizontal channel regions,
wherein the ferroelectric layer is between the vertical word line and the plurality of metal containing patterns, wherein
an inner surface of the ferroelectric layer is in contact with the vertical word line, and a local surface of an outer surface of the ferroelectric layer, which faces the plurality of horizontal channel regions, is in contact with the metal-containing pattern.
5 . The three-dimensional non-volatile memory device of claim 1 , wherein the memory cell array further comprises:
a plurality of inter-cell insulation patterns respectively one by one between the plurality of horizontal channel regions, the plurality of inter-cell insulation patterns overlapping the plurality of horizontal channel regions in the vertical direction; and
a gate dielectric film structure between the vertical word line and the plurality of horizontal channel regions, the gate dielectric film structure comprising a tunneling dielectric film, a charge storage film, and a blocking dielectric film, which are sequentially arranged in a direction toward the vertical word line from an inner surface of each of the plurality of horizontal channel regions, and wherein
at least one of the tunneling dielectric film, the charge storage film, and the blocking dielectric film passes through the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction.
6 . The three-dimensional non-volatile memory device of claim 1 , wherein the memory cell array further comprises:
a plurality of inter-cell insulation patterns respectively one by one between the plurality of horizontal channel regions, the plurality of inter-cell insulation patterns overlapping the plurality of horizontal channel regions in the vertical direction; and
a plurality of gate dielectric film structures between the vertical word line and the plurality of horizontal channel regions, each of the plurality of gate dielectric film structures comprises:
a tunneling dielectric film,
a charge storage film, and
a blocking dielectric film, which are sequentially arranged in a direction toward
the vertical word line from an inner surface of each of the plurality of horizontal
channel regions, and wherein
at least one of the tunneling dielectric film, the charge storage film, and the blocking dielectric film has a maximum vertical length, which is defined by two inter-cell insulation patterns, which are adjacent to each other in the vertical direction, from among the plurality of inter-cell insulation patterns.
7 . The three-dimensional non-volatile memory device of claim 1 , wherein the memory cell array further comprises a plurality of conductive lines extending in the second lateral direction on the substrate, the plurality of conductive lines overlapping each other and apart from each other in the vertical direction, and wherein
each of the plurality of conductive lines is in contact with a selected one of the plurality of horizontal channel regions.
8 . A three-dimensional non-volatile memory device comprising:
a substrate having a main surface;
a plurality of horizontal channel regions overlapping each other and apart from each other in a vertical direction on the substrate, each horizontal channel region extending parallel to the main surface of the substrate;
a plurality of inter-cell insulation patterns respectively one by one between the plurality of horizontal channel regions;
a plurality of vertical word lines passing through the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction,
each of the plurality of horizontal channel regions comprising a plurality of ring channel portions regularly arranged in a first lateral direction and a plurality of connection portions respectively between the plurality of ring channel portions, the plurality of ring channel portions defining a plurality of first local holes located apart from each other,
the plurality of inter-cell insulation patterns comprising a plurality of second local holes, which are aligned with the plurality of first local holes in the vertical direction, and
the plurality of vertical word lines passing through the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction via the plurality of first local holes and the plurality of second local holes; and
a plurality of ferroelectric layers passing through the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction via the plurality of first local holes and the plurality of second local holes.
9 . The three-dimensional non-volatile memory device of claim 8 , wherein the plurality of vertical word lines are arranged in a straight line in the first lateral direction.
10 . The three-dimensional non-volatile memory device of claim 8 , wherein the plurality of vertical word lines are arranged in zigzag in the first lateral direction.
11 . The three-dimensional non-volatile memory device of claim 8 , further comprising:
a plurality of interface dielectric layers surrounding outer sidewalls of the plurality of ferroelectric layers inside the plurality of first local holes,
wherein each of the plurality of ferroelectric layers is in contact with an outer sidewall of a selected one of the plurality of vertical word lines.
12 . The three-dimensional non-volatile memory device of claim 8 , further comprising:
a plurality of metal-containing patterns surrounding outer sidewalls of the plurality of ferroelectric layers inside the plurality of first local holes, wherein
each of the plurality of metal-containing patterns has a maximum vertical length, which is defined by two inter-cell insulation patterns, which are adjacent to each other in the vertical direction, from among the plurality of inter-cell insulation patterns.
13 . The three-dimensional non-volatile memory device of claim 8 , further comprising:
a plurality of gate dielectric film structures surrounding outer surfaces of the plurality of vertical word lines inside the plurality of first local holes, and wherein
each of the plurality of gate dielectric film structures comprises a tunneling dielectric film, a charge storage film, and a blocking dielectric film, which are sequentially arranged in a direction toward one of the plurality of vertical word lines from an inner surface of a corresponding ring channel portion of each of the plurality of horizontal channel regions, and
at least one of the tunneling dielectric film, the charge storage film, and the blocking dielectric film passes through the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction via the plurality of first local holes and the plurality of second local holes.
14 . The three-dimensional non-volatile memory device of claim 8 , further comprising:
a plurality of gate dielectric film structures surrounding outer surfaces of the plurality of vertical word lines inside the plurality of first local holes, and wherein
each of the plurality of gate dielectric film structures comprises a tunneling dielectric film, a charge storage film, and a blocking dielectric film, which are sequentially arranged in a direction toward one of the plurality of vertical word lines from an inner surface of the ring channel portion of each of the plurality of horizontal channel regions, and
at least one of the tunneling dielectric film, the charge storage film, and the blocking dielectric film has a maximum vertical length, which is defined by two adjacent ones of the plurality of inter-cell insulation patterns.
15 . A three-dimensional non-volatile memory device comprising:
a substrate having a main surface;
a memory cell array comprising a plurality of memory cell strings, each memory cell string extending in a first lateral direction that is parallel to the main surface of the substrate, the plurality of memory cell strings being repeatedly arranged in a second lateral direction and a vertical direction, wherein the second lateral direction is parallel to the main surface of the substrate and perpendicular to the first lateral direction, and the vertical direction is perpendicular to the main surface of the substrate;
a plurality of bit lines, each bit line being connected to one side of a corresponding one of the plurality of memory cell strings, the plurality of bit lines overlapping each other and apart from each other in the vertical direction; and
at least one source line apart from the plurality of bit lines with the plurality of memory cell strings therebetween in the first lateral direction, the at least one source line being connected to another side of each of the plurality of memory cell strings,
each of the plurality of memory cell strings comprising:
a horizontal channel region comprising a plurality of ring channel portions regularly arranged in the first lateral direction and a plurality of connection portions respectively between the plurality of ring channel portions, the plurality of ring channel portions defining a plurality of local holes located apart from each other;
a plurality of vertical word lines passing through the horizontal channel region in the vertical direction via the plurality of local holes; and
a plurality of ferroelectric layers passing through the horizontal channel region in the vertical direction via the plurality of local holes.
16 . The three-dimensional non-volatile memory device of claim 15 , wherein
each of the plurality of bit lines is shared among a first group of memory cell strings, which are at the same vertical level on the main surface of the substrate, and
each of the plurality of ferroelectric layers is in contact with an outer sidewall of a selected one of the plurality of vertical word lines.
17 . The three-dimensional non-volatile memory device of claim 15 , wherein each of the plurality of vertical word lines is shared among a second group of memory cell strings, which overlap each other in the vertical direction, from among the plurality of memory cell strings.
18 . The three-dimensional non-volatile memory device of claim 15 , wherein the at least one source line comprises a common source line connected to another side of each of the plurality of memory cell strings.
19 . The three-dimensional non-volatile memory device of claim 15 , wherein
the at least one source line comprises a plurality of source lines, each source line being connected to one side of a corresponding one of the plurality of memory cell strings, the plurality of source lines overlapping each other and apart from each other in the vertical direction, and
each of the plurality of source lines is shared among a first group of memory cell strings at the same vertical level on the main surface of the substrate.
20 . The three-dimensional non-volatile memory device of claim 15 , further comprising:
a peripheral circuit structure between the substrate and the memory cell array, the peripheral circuit structure comprising a plurality of transistors and a plurality of wiring structures connected to the plurality of transistors, and wherein
the plurality of wiring structures comprise at least one conductive line connected to at least one of the plurality of vertical word lines.