IP Library › Granted Patent US 12,563,747
Granted Patent B2
US 12,563,747 · App. 18/059,672 · Granted Feb 24, 2026

Three dimensional ReRAM device

Inventors: Min Gyu Sung (Latham, NY); Soon-Cheon Seo (Glenmont, NY); Heng Wu (Santa Clara, CA); Julien Frougier (Albany, NY); Chen Zhang (Guilderland, NY); Ruilong Xie (Niskayuna, NY)
Assignee: International Business Machines Corporation
H10B63/845H10N70/063
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,563,747
App. No.
18/059,672
Granted
Feb 24, 2026
Kind
B2
Abstract

A resistive random access memory (ReRAM) device and a method for forming the device are provided. The ReRAM device includes a first electrode, a resistive switching element layer in contact with the first electrode, and a plurality of second electrodes in contact with the resistive switching element layer. Protruding portions of the first electrode and the resistive switching element layer overlap with the plurality of second electrodes in a vertical direction of the ReRAM device to form a plurality of vertically stacked ReRAM cells.

Claims (15)

1 . A resistive random access memory (ReRAM) device comprising:

a first electrode;

a resistive switching element layer in contact with the first electrode; and

a plurality of second electrodes in contact with the resistive switching element layer,

wherein protruding portions of the first electrode and the resistive switching element layer overlap with the plurality of second electrodes in a vertical direction on a first side of the ReRAM device to form a plurality of vertically stacked ReRAM cells,

wherein the plurality of ReRAM cells have a stepped configuration on a second side of the ReRAM device, and

wherein a first contact is formed in contact with the first electrode and second contacts are formed in contact with each of the second electrodes for each of the respective ReRAM cells.

2 . The ReRAM device of claim 1 , wherein for each ReRAM cell, a portion of the second electrode that is not overlapped with the first electrode in the vertical direction is sandwiched between dielectric layers.

3 . The ReRAM device of claim 2 , wherein the dielectric layers have a higher etching selectivity relative to the second electrodes.

4 . The ReRAM device of claim 2 , wherein the dielectric layers are recessed in a lateral direction relative to the second electrodes.

5 . The ReRAM device of claim 1 , wherein the resistive switching layer includes a high-material.

6 . The ReRAM device of claim 1 , the first contact is a shared bit line that is in contact with the first electrode.

7 . The ReRAM device of claim 1 , wherein the second contacts are a plurality of word lines, each word line connected to one of the plurality of second electrodes.

8 . The ReRAM device of claim 1 , further comprising an interlayer dielectric layer separating a first group of the ReRAM cells from a second group of the ReRAM cells and dividing the first electrode into a first ReRAM cell group electrode and a second ReRAM cell group electrode.

9 . The ReRAM device of claim 8 , further comprising a plurality of first contacts that include a first bit line connected to the first ReRAM cell group electrode and a second bit line connected to the second ReRAM cell group electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2022
From: SUNG, MIN GYU; SEO, SOON-CHEON; WU, HENG; FROUGIER, JULIEN; ZHANG, CHEN; XIE, RUILONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 061908/0598 →
Continuity (1)
Related Publication 20240179924A1 · May 30, 2024
References Cited (28)
US 8923050B2 · Cernea et al. · 2014 [cited by applicant]
US 9054307B2 · Wang et al. · 2015 [cited by applicant]
US 9466794B2 · Yang et al. · 2016 [cited by applicant]
US 9595566B2 · Takaki · 2017 [cited by applicant]
US 9761800B2 · Phatak · 2017 [cited by applicant]
US 11088203B2 · Hsieh · 2021 [cited by applicant]
US 11196000B2 · Kim et al. · 2021 [cited by applicant]
US 20130094273A1 · Chien et al. · 2013 [cited by applicant]
US 20170053906A1 · Or-Bach et al. · 2017 [cited by applicant]
US 20170154845A1 · Takaki · 2017 [cited by applicant]
US 20180158947A1 · Yeh · 2018 [cited by examiner]
US 20200144496A1 · Glassman · 2020 [cited by applicant]
US 20210167128A1 · Ando et al. · 2021 [cited by applicant]
US 20210242239A1 · Lin · 2021 [cited by applicant]
US 20210313512A1 · Cai · 2021 [cited by examiner]
US 20220051698A1 · Han · 2022 [cited by applicant]
US 20240147877A1 · Lung · 2024 [cited by examiner]
CN 114284295A · 2022 [cited by applicant]
JP 5369071B2 · 2013 [cited by applicant]
JP 2018198321A · 2018 [cited by applicant]
KR 20190110504A · 2019 [cited by applicant]
WO 2014194069A2 · 2014 [cited by applicant]
Chen et al., “HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector,” IEEE Xplore, 2012, pp. 20.7.1-20.7.4. [cited by applicant]
Deng et al., “Design and Optimization Methodology for 3D RRAM Arrays,” IEEE Xplore, 2013, pp. 25.7.1-25.7.4. [cited by applicant]
Lee et al., “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” IEEE Xplore, 2007, pp. 771-774. [cited by applicant]
Sung et al., “Development of 1T-1R cross bar test vehicle for RRAM technology on 300mm wafers,” Sematech, 2008, 20 pages. [cited by applicant]
Tseng et al., “Solving the Scaling Issue of Increasing Forming Voltage in Resistive Random Access Memory Using High-k Spacer Structure,” Advanced Electronic Materials, Sep. 2017, 8 pages. [cited by applicant]
Ye et al., “Ultimate vertical gate-all-around metal-oxide-semiconductor field-effect transistor and its three-dimensional integrated circuits,” Materials Science in Semiconductor Processing, Jul. 1, 2021, 10 pages, vol.… [cited by applicant]