Method for porosifying a material and semiconductor structure
A method for porosifying a III-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×10 17 cm −3 , beneath a surface layer of a second III-nitride material, having a charge carrier density of between 1×10 14 cm −3 and 1×10 17 cm −3 . The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first III-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.
1 . A semiconductor structure comprising:
a porous sub-surface structure of a first III-nitride material; and
a non-porous surface layer of a second III-nitride material; the surface layer having a charge carrier density of between 1×10 14 cm −3 and 1×10 17 cm 31 3 ;
in which the sub-surface structure has porosity throughout the porous sub-surface structure, the surface layer having a lateral width and the sub-surface structure having a lateral width, in which the lateral width of the surface layer at a narrowest point thereof is more than 550 μm, and in which the lateral width of the sub-surface structure at a narrowest point thereof is more than 550 μm.
2 . The semiconductor structure according to claim 1 , in which the surface layer completely covers the sub-surface structure.
3 . The semiconductor structure according to claim 1 , in which the surface layer has a minimum lateral dimension of at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.
4 . The semiconductor structure according to claim 1 , in which the surface layer and the sub-surface structure comprise III-nitride materials selected from the list consisting of: GaN, AlGaN, InGaN, and AlInGaN.
5 . The semiconductor structure according to claim 1 , in which a threading dislocation density in both the surface layer and the sub-surface structure is at least 1×10 4 cm −2 , 1×10 5 cm −2 , 1×10 6 cm −2 , 1×10 7 cm − 2 , or 1×10 8 cm −2 and/or less than 1×10 9 cm −2 or 1×10 10 cm −2 .
6 . The semiconductor structure according to claim 1 , in which a thickness of the surface layer is at least 1 nm, or 10 nm, or 100 nm, and/or less than 1 μm, or 5 μm, or 10 μm.
7 . The semiconductor structure according to claim 1 , in which the porous sub-surface structure has an average pore size of greater than 1 nm, or 2 nm, or 10 nm, or 20 nm, and/or less than 50 nm, or 60 nm, or 70 nm.
8 . The semiconductor structure according to claim 1 , comprising a plurality of sub-surface layers formed from III-nitride material in the form of a stack of layers; in which odd-numbered sub-surface layers (counting away from the surface layer) are porous, with uniform porosity throughout each layer, and even-numbered sub-surface layers are non-porous.
9 . The semiconductor structure according to claim 8 , in which each odd sub-surface layer has the same porosity, and each even layer is non-porous, such that the structure acts as a distributed Bragg reflector (DBR).
10 . The semiconductor structure according to claim 8 , in which at least two odd sub-surface layers have different porosities.
11 . The semiconductor structure according to claim 1 , in which the semiconductor structure is not patterned with trenches.
12 . The semiconductor structure according to claim 1 , in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm.
13 . The semiconductor structure according to claim 1 , in which an outermost surface of the surface layer has a root mean square roughness of less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm, over an area of 1micrometer squared.
14 . The semiconductor structure according to claim 1 , in which the surface layer is not coated with an electrically insulating layer.
15 . A method of manufacturing a semiconductor device, the method comprising overgrowing a semiconductor device on the semiconductor structure of claim 1 .
16 . The method of claim 15 , in which the semiconductor device of claim 15 is a laser or a light emitting diode.
17 . A device incorporating or mounted on the semiconductor structure of claim 1 .
18 . A semiconductor structure comprising:
a porous sub-surface structure of a first III-nitride material; and
a surface layer of a second III-nitride material; the surface layer having a charge carrier density of between 1×10 14 cm 31 3 and 1×10 17 cm −3 ;
in which the porous sub-surface structure has porosity throughout the porous sub-surface structure, the surface layer having a lateral width and the porous sub-surface structure having a lateral width, in which the lateral width of the surface layer at a narrowest point thereof is more than 550 μm, and in which the lateral width of the porous sub-surface structure at a narrowest point thereof is more than 550 μm.
19 . A semiconductor structure comprising:
a porous sub-surface structure of a first III-nitride material; and
a non-porous surface layer of a second III-nitride material; the surface layer having a charge carrier density of between 1×10 14 cm −3 and 1×10 17 cm −3 ;
in which the porous sub-surface structure is porous throughout the sub-surface structure,
in which the surface layer has a plurality of lateral dimensions and a minimum lateral dimension which is the smallest of those lateral dimensions,
in which the porous sub-surface structure has a plurality of lateral dimensions and a minimum lateral dimension which is the smallest of those lateral dimensions,
in which the minimum lateral dimension of the surface layer is more than 550μm, and in which the minimum lateral dimension of the porous sub-surface structure is more than 550 μm.
20 . A device incorporating or mounted on the semiconductor structure of claim 19 .