Method for electrochemically etching a semiconductor structure
A method for etching a semiconductor structure ( 110 ) is provided, the semiconductor structure comprising a sub-surface quantum structure ( 30 ) of a first III-V semiconductor material, beneath a surface layer ( 31 ) of a second III-V semiconductor material having a charge carrier density of less than 5×10 17 cm −3 . The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte ( 130 ), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure ( 30 ) to form a plurality of nanostructures, while the surface layer ( 31 ) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.
1. A semiconductor structure comprising:
a porous nanostructured portion comprising a plurality of sub-surface nanostructures of a first III-V semiconductor material; and
a surface layer of a second III-V semiconductor material, the surface layer having a charge carrier density of less than 5×10 17 cm −3 ;
in which the surface layer covers the porous nanostructured portion comprising the sub-surface nanostructures,
in which the sub-surface nanostructures in the porous nanostructured portion are light-emitting quantum nanostructures.
2. The semiconductor structure according to claim 1 , in which the surface layer completely covers the sub-surface nanostructures.
3. The semiconductor structure according to claim 1 , in which the surface layer has a minimum lateral dimension of at least 1 μm, or 10 μm, or 50 μm, or 100 μm, or 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.
4. The semiconductor structure according to claim 1 , in which the porous nanostructured portion has a minimum lateral dimension of at least 500 nm, 1 μm, 5 μm, 45 μm, 95 μm, or 1 mm, or at least 10 mm, or 5 cm, or 15 cm, or 20 cm.
5. The semiconductor structure according to claim 1 , in which the surface layer and the sub-surface nanostructures comprise III-nitride materials selected from the list consisting of: GaN, InN, AlGaN, InGaN, InAlN and AlInGaN.
6. The semiconductor structure according to claim 1 , in which the thickness of the surface layer is at least 40 nm, or 50 nm, or 100 nm, and/or less than 1 μm, or 5 μm, or 10 μm.
7. The semiconductor structure according to claim 1 , in which the porous nanostructured portion has an average pore size of greater than 1 nm, or 2 nm, or 10 nm, or 20 nm, and/or less than 50 nm, or 60 nm, or 70 nm.
8. The semiconductor structure according to claim 1 , comprising a plurality of sub-surface layers of nanostructures in the form of a stack of layers; in which sub-surface layers of nanostructures are separated by intermediate barrier layers of non-porous III-V semiconductor material.
9. The semiconductor structure according to claim 1 , in which the semiconductor structure is not patterned with trenches, or in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm.
10. The semiconductor structure according to claim 1 , in which an outermost surface of the surface layer has a root mean square roughness of less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm, over an area of 1 micrometer squared.
11. The semiconductor structure according to claim 1 , in which the surface layer is not coated with an electrically insulating layer.
12. The semiconductor structure according to claim 1 , in which the light-emitting quantum nanostructures are quantum dots.
13. The semiconductor structure according to claim 1 , in which the semiconductor structure is an LED structure, and the light-emitting quantum nanostructures form a sub-surface layer of quantum dots.
14. The semiconductor structure according to claim 1 , in which the surface layer of the second III-V semiconductor material has a charge carrier density of less than 4×10 17 cm −3 , or less than 3×10 17 cm −3 , or less than 2×10 17 cm −3 , or less than 1×10 17 cm −3 .
15. A device incorporating or mounted on the semiconductor structure as defined in claim 1 .
16. The semiconductor structure according to claim 1 , wherein both the surface layer and the porous nanostructured portion have a minimum lateral dimension of more than 550 μm.
17. A semiconductor structure comprising:
a porous nanostructured portion comprising a plurality of sub-surface nanostructures of a first III-V semiconductor material; and
a surface layer of a second III-V semiconductor material, the surface layer having a charge carrier density of less than 5×10 17 cm −3 ;
in which the surface layer covers the porous nanostructured portion comprising the sub-surface nanostructures; and
in which the porous nanostructured portion is a porous quantum structure, the porous nanostructured portion having one or more dimensions of less than or equal to 0.25 nm, or 0.5 nm, or 1 nm, or 2 nm, or 3 nm, or 5 nm, or 8 nm, or 10 nm, or 12 nm.
18. The semiconductor structure according to claim 17 , in which the porous nanostructured portion is a porous quantum structure, the porous nanostructured portion having a thickness greater than or equal to 1 nm, or 2 nm, or 3 nm, or 5 nm, and/or less than 6 nm, or 7 nm, or 8 nm, or 9 nm, or 10 nm, or 12 nm.
19. A semiconductor structure comprising:
a porous nanostructured portion comprising a plurality of sub-surface nanostructures of a first III-V semiconductor material; and
a surface layer of a second III-V semiconductor material, the surface layer having a charge carrier density of less than 5×10 17 cm −3 ;
in which the surface layer covers the porous nanostructured portion comprising the sub-surface nanostructures; and
in which the semiconductor structure is an LED structure, and the porous nanostructured portion is a porous quantum well.