IP Library Granted Patent US 11,942,549
Granted Patent B2
US 11,942,549 · App. 18/064,562 · Granted Mar 26, 2024

Semiconductor device and method of manufacture

Inventors: Wan-Yi Kao (Baoshan Township, TW); Yu-Cheng Shiau (Hsinchu, TW); Chunyao Wang (Zhubei, TW); Chih-Tang Peng (Zhubei, TW); Yung-Cheng Lu (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/785H01L21/0214H01L21/02211H01L21/02263H01L21/76224H01L21/76232H01L21/823481H01L27/0924H01L29/517H01L29/66545H01L29/66795H01L29/66818H01L21/76227
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Quick Facts
Patent No.
US 11,942,549
App. No.
18/064,562
Granted
Mar 26, 2024
Kind
B2
Abstract

A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Claims (51)

1. A method of manufacturing a semiconductor device, the method comprising:

lining a semiconductor fin with a first liner;

lining the semiconductor fin with a second liner different from the first liner;

lining the semiconductor fin with a third liner different from the second liner;

annealing the third liner to form silicon oxide;

lining the semiconductor fin with a fourth liner different from the third liner;

depositing a capping layer over the fourth liner;

annealing the capping layer to transform the capping layer to silicon oxide;

depositing a dielectric cap over the capping layer;

planarizing the dielectric cap to the semiconductor fin; and

exposing a sidewall of the semiconductor fin.

2. The method of claim 1 , wherein the annealing the third liner comprises:

performing a first wet annealing process;

performing a second wet annealing process with different parameters from the first wet annealing process; and

a dry annealing process.

3. The method of claim 2 , wherein the first wet annealing process is performed at least in part at a temperature of between about 300° C. and about 500° C. for a time of between about 0.5 hours and about 2 hours.

4. The method of claim 3 , wherein the second wet annealing process is performed at least in part at a temperature of between about 500° C. and about 650° C. for a time of between about 0.5 hours and about 4 hours.

5. The method of claim 4 , wherein the dry annealing process is performed at least in part at a temperature of between about 600° C. and about 750° C. for a time of between about 0.5 hours and about 2 hours.

6. The method of claim 1 , wherein the annealing the third liner decreases a number of nitrogen bonds in the third liner.

7. The method of claim 1 , wherein the annealing the third line increases a number of oxygen bonds in the third liner.

8. A method of manufacturing a semiconductor device, the method comprising:

forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate;

forming a first liner adjacent to both the first semiconductor fin and the second semiconductor fin;

forming a second liner over the first liner;

forming a third liner over the second liner, the third liner comprising nitrogen at a percentage of less than about 10%;

forming a fourth liner over the third liner;

forming a capping layer over the fourth liner, the capping layer comprising carbon at a percentage of less than about 10%; and

depositing a dielectric cap over the capping layer, wherein the first semiconductor fin extends further away from the semiconductor substrate than the dielectric cap.

9. The method of claim 8 , wherein the forming the third liner comprises:

depositing a first material of the third liner; and

removing nitrogen from the first material.

10. The method of claim 9 , wherein the removing the nitrogen is performed at least in part with an annealing process.

11. The method of claim 10 , wherein the annealing process comprises:

a first wet annealing process;

a second wet annealing process different from the first wet annealing process; and

a dry annealing process.

12. The method of claim 11 , wherein the first wet annealing process is performed at least in part at a temperature of between about 300° C. and about 500° C.

13. The method of claim 12 , wherein the second wet annealing process is performed at least in part at a temperature of between about 500° C. and about 650° C.

14. The method of claim 8 , wherein the forming the third liner comprises:

depositing a first material of the third liner; and

increasing a number of oxygen bonds in the first material.

15. A method of manufacturing a semiconductor device, the method comprising:

depositing a first liner to line a recess adjacent to a first semiconductor fin, the first liner comprising a first material;

wet annealing the first liner to form a second material different from the first material;

depositing a second liner over the second material, the second liner comprising a third material; and

annealing the second liner to form a fourth material different from the third material.

16. The method of claim 15 , wherein the first material is silicon oxynitride.

17. The method of claim 16 , wherein the second material is silicon oxide.

18. The method of claim 17 , wherein the third material is silicon oxycarbonitride.

19. The method of claim 18 , wherein the fourth material is silicon oxide.

20. The method of claim 15 , wherein the wet annealing the first liner is performed at least in part at a temperature of between about 300° C. and about 500° C.

Continuity (3)
Continuation 17157330 · Jan 25, 2021
Provisional Application 63055045 · Jul 22, 2020
Related Publication 20230103640A1 · Apr 6, 2023