IP Library › Granted Patent US 12,255,534
Granted Patent B2
US 12,255,534 · App. 18/066,893 · Granted Mar 18, 2025

Systems and methods for stable intermediate node operation in series stacked phase DC-DC converters

Inventor: Richard Nicholson (Aptos, CA)
Assignee: Empower Semiconductor, Inc.
H02M3/158H02M1/0074H02M1/0009H02M3/1582H02M3/1584
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Quick Facts
Patent No.
US 12,255,534
App. No.
18/066,893
Granted
Mar 18, 2025
Kind
B2
Abstract

A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to continuously operate the first buck converter, sense a voltage at the junction, compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage disables the second buck converter. In yet another aspect, the control circuit is arranged to continuously operate the first buck converter, compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

Claims (47)

1. A power converter circuit comprising:

a first buck converter including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal coupled to the second drain terminal at a first switch node;

a second buck converter including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal;

an input terminal coupled to the first drain terminal;

an output terminal coupled to the first and second switch nodes; and

a control circuit coupled to each of the first and second buck converters, and arranged to continuously operate the first buck converter, wherein the control circuit is further arranged to:

sense a voltage at the junction;

compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage, the control circuit disables the second buck converter; and

compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

2. The power converter circuit of claim 1 , wherein the first and second buck converters are arranged to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

3. The power converter circuit of claim 1 , wherein the first and second buck converters are arranged to control power transfer from the input terminal to the output terminal.

4. The power converter circuit of claim 1 , wherein the control circuit comprises a window comparator that includes a first comparator and a second comparator.

5. The power converter circuit of claim 4 , wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

6. The power converter circuit of claim 5 , wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

7. The power converter circuit of claim 5 , wherein the output terminal is coupled to the first switch node through a first inductor.

8. The power converter circuit of claim 7 , wherein the first inductor is coupled to the first switch node through a first capacitor.

9. The power converter circuit of claim 8 , wherein a second capacitor is coupled to the junction at its first terminal and to a ground at its second terminal.

10. The power converter circuit of claim 5 , wherein the output terminal is coupled to the second switch node through a second inductor.

11. A method of operating a power converter circuit, the method including:

providing a first buck converter including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal coupled to the second drain terminal at a first switch node;

providing a second buck converter including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal;

providing an input terminal coupled to the first drain terminal;

providing an output terminal coupled to the first and second switch nodes; and

providing a control circuit coupled to each of the first and second buck converters;

continuously operating, by the control circuit, the first buck converter;

sensing, by the control circuit, a voltage at the junction;

comparing, by the control circuit, the sensed voltage to a first threshold voltage;

disabling, by the control circuit, the second buck converter in response to the sensed voltage being at a voltage lower than the first threshold voltage;

comparing, by the control circuit, the sensed voltage to a second threshold voltage; and

operating, by the control circuit, the second buck converter in response to the sensed voltage being at a voltage higher than the second threshold voltage.

12. The method of claim 11 , further comprising generating, by the first and second buck converters, an output voltage at the output terminal that is lower than an input voltage at the input terminal.

13. The method of claim 11 , further comprising controlling power transfer, by the first and second buck converters, from the input terminal to the output terminal.

14. The method of claim 11 , wherein the control circuit comprises a window comparator that includes a first comparator and a second comparator.

15. The method of claim 14 , wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

16. The method of claim 15 , wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

17. A circuit comprising:

a first buck converter having a first switch node;

a second buck converter having a second switch node and coupled in series to the first buck converter at a junction;

an input terminal coupled to the first buck converter;

an output terminal coupled to the first and second switch nodes; and

a control circuit coupled to each of the first and second buck converters, and arranged to continuously operate the first buck converter, wherein the control circuit is further arranged to:

sense a voltage at the junction;

compare the sensed voltage to a first threshold voltage and in response to the sensed voltage being at a voltage lower than the first threshold voltage, disables the second buck converter; and

compare the sensed voltage to a second threshold voltage and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter.

18. The circuit of claim 17 , wherein the first and second buck converters are arranged to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

19. The circuit of claim 17 , wherein the first and second buck converters are arranged to control power transfer from the input terminal to the output terminal.

20. The circuit of claim 17 , wherein the control circuit comprises a window comparator that includes a first comparator and a second comparator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2023
From: NICHOLSON, RICHARD
To: EMPOWER SEMICONDUCTOR, INC.
Reel/Frame 064019/0338 →
Continuity (3)
Provisional Application 63265823 · Dec 21, 2021
Provisional Application 63265611 · Dec 17, 2021
Related Publication 20230198390A1 · Jun 22, 2023
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