Strong ordered transaction for DMA transfers
A technique for processing strong ordered transactions in a direct memory access engine may include retrieving a memory descriptor to perform a strong ordered transaction, and delaying the strong ordered transaction until pending write transactions associated with previous memory descriptors retrieved prior to the memory descriptor are complete. Subsequent transactions associated with memory descriptors following the memory descriptor are allowed to be issued while waiting for the pending write transactions to complete. Upon completion of the pending write transactions, the strong ordered transaction is performed.
1. A computer-implemented method performed by a direct memory access (DMA) engine, comprising:
processing a first memory descriptor to perform a first DMA write transaction associated with a first set of data;
processing a second memory descriptor retrieved after retrieval of the first memory descriptor to perform a second DMA write transaction to update a semaphore to indicate that the first set of data has been written, the second memory descriptor having a strong ordered indicator bit enabled to indicate that the second DMA write transaction is a strong ordered transaction that is to be performed after pending DMA write transactions associated with memory descriptors retrieved before retrieval of the second memory descriptor are complete;
delaying, based on the strong ordered indicator bit being enabled in the second memory descriptor, performance of the second DMA write transaction until the first set of data has been written;
processing a third memory descriptor retrieved after retrieval of the second memory descriptor to perform a third DMA write transaction to write a second set of data, the third memory descriptor having a strong ordered indicator bit disabled;
performing the third DMA write transaction to write the second set of data before performing the second DMA write transaction; and
upon completion of the first DMA write transaction, performing the second DMA write transaction associated with the second memory descriptor to update the semaphore.
2. The computer-implemented method of claim 1 , further comprising:
tracking, based on the strong ordered indicator bit being set in the second memory descriptor, progress of the first DMA write transaction in a scoreboard.
3. The computer-implemented method of claim 2 , wherein the scoreboard includes a dependency vector of pending DMA write transactions for each outstanding strong ordered transaction.
4. The computer-implemented method of claim 1 , wherein the first DMA write transaction is complete when an acknowledgement for the first DMA write transaction is received.
5. A computer-implemented method comprising:
retrieving a first memory descriptor in a direct memory access (DMA) engine to perform a strong ordered transaction, wherein the strong ordered transaction is to be performed after completion of pending DMA write transactions associated with memory descriptors retrieved prior to retrieval of the first memory descriptor are complete;
delaying performance of the strong ordered transaction associated with the first memory descriptor until the pending DMA write transactions associated with the memory descriptors retrieved prior to retrieval of the first memory descriptor are complete;
allowing subsequent DMA transactions associated with memory descriptors retrieved after retrieval of the first memory descriptor to be issued while waiting for the pending DMA write transactions associated with memory descriptors retrieved prior to retrieval of the first memory descriptor to complete; and
upon completion of the pending DMA write transactions associated with memory descriptors retrieved prior to retrieval of the first memory descriptor, performing the strong ordered transaction associated with the first memory descriptor.
6. The computer-implemented method of claim 5 , further comprising maintaining a scoreboard to track progress of each pending DMA write transaction that the strong ordered transaction is dependent on.
7. The computer-implemented method of claim 6 , wherein the scoreboard includes a dependency vector of pending DMA write transactions for each outstanding strong ordered transaction.
8. The computer-implemented method of claim 5 , wherein the pending DMA write transactions that the strong ordered transaction waits for include DMA write transactions from multiple write descriptor queues in the DMA engine.
9. The computer-implemented method of claim 5 , wherein the first memory descriptor has a strong ordered indicator bit to indicate that the first memory descriptor is for a strong ordered transaction.
10. The computer-implemented method of claim 5 , wherein the strong ordered transaction is a strong ordered write transaction.
11. The computer-implemented method of claim 10 , wherein the strong ordered write transaction is a write transaction to update a semaphore.
12. The computer-implemented method of claim 10 , further comprising:
retrieving an additional memory descriptor to perform an additional strong ordered transaction while the strong ordered write transaction is still pending;
delaying the additional strong ordered transaction until each DMA write transaction pending before the additional memory descriptor, including the strong ordered write transaction, are complete; and
allowing DMA transactions associated with memory descriptors following the additional memory descriptor to be issued while waiting for each DMA write transaction pending before the additional memory descriptor, including the strong ordered write transaction, to complete.
13. The computer-implemented method of claim 5 , wherein the strong ordered transaction is a strong ordered read transaction.
14. The computer-implemented method of claim 5 , wherein a pending DMA write transaction is complete when an acknowledgement is received in response to the pending DMA write transaction.
15. A direct memory access (DMA) engine comprising:
one or more descriptor queues operable to store memory descriptors associated with transactions;
a scoreboard to indicate progress of pending transactions for completion; and
a controller operable to:
retrieve, from a descriptor queue of the one or more descriptor queues, a first memory descriptor to perform a strong ordered transaction, wherein the strong ordered transaction is to be performed after pending DMA write transactions associated with memory descriptors retrieved prior to retrieval of the first memory descriptor are complete;
delay the strong ordered transaction associated with the first memory descriptor until the pending DMA write transactions associated with the memory descriptors retrieved prior to retrieval of the first memory descriptor are complete as indicated by the scoreboard;
allow subsequent DMA transactions associated with memory descriptors retrieved after retrieval of the first memory descriptor to be issued while waiting for the pending DMA write transactions to complete; and
upon completion of the pending DMA write transactions associated with the memory descriptors retrieved prior to retrieval of the first memory descriptor, perform the strong ordered transaction associated with the first memory descriptor.
16. The DMA engine of claim 15 , wherein the first memory descriptor includes a strong ordered indicator bit to indicate the strong ordered transaction.
17. The DMA engine of claim 15 , wherein the pending DMA write transactions belong to more than one descriptor queue.
18. The DMA engine of claim 15 , wherein the strong ordered transaction is a strong ordered write transaction.
19. The DMA engine of claim 15 , wherein the strong ordered transaction is a strong ordered read transaction.
20. The DMA engine of claim 15 , wherein the pending DMA write transactions are associated with writing a tensor into a buffer of a neural network processor.