IP Library › Granted Patent US 11,907,575
Granted Patent B2
US 11,907,575 · App. 17/483,083 · Granted Feb 20, 2024

Memory controller and memory control method

Inventors: Hosang Yoon (Yongin-si, KR); Seungwon Lee (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F3/0659G06F3/0604G06F3/0656G06F3/0679
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Quick Facts
Patent No.
US 11,907,575
App. No.
17/483,083
Granted
Feb 20, 2024
Kind
B2
Abstract

A memory controller includes: a first buffer configured to receive a memory request from a host and store therein the received memory request; a command generator configured to generate a first command corresponding to the memory request, and set a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory; a second buffer configured to store therein a plurality of commands comprising the first command; and a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.

Claims (57)

1. A memory controller comprising:

a first buffer configured to receive a memory request from a host and store therein the received memory request;

a command generator configured to generate a first command corresponding to the memory request, and set a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory or a general memory;

a second buffer configured to store therein a plurality of commands comprising the first command; and

a command scheduler configured to:

maintain an order of the first command among commands corresponding to the PIM memory stored in the second buffer, in response to the type of the first command indicating the PIM memory; and

change the order of the first command among the commands corresponding to the general memory, in response to the type indicating the general memory.

2. The memory controller of claim 1 , wherein

the memory request comprises a field indicating the address,

the field comprises an area separating bit that separates an address of the general memory and an address of the PIM memory, and

for the setting of the type of the first command, the command generator is configured to set the type of the first command based on the area separating bit.

3. A memory controller comprising:

a first buffer configured to receive a memory request from a host and store therein the received memory request;

a request arbiter configured to:

set a type of a first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory or a general memory;

maintain an order of the memory request among memory requests corresponding to the PIM memory to be transferred to a command generator in response to the type of the first command indicating the PIM memory; and

change the order of the memory request among the memory requests corresponding to the general memory, in response to the type indicating the general memory;

the command generator, wherein the command generator is configured to generate the first command corresponding to the memory request and the type of the first command based on the order of the memory request;

a second buffer configured to store therein a plurality of commands comprising the first command; and

a command scheduler configured to determine whether to change an order of the first command stored in the second buffer based on the type of the first command.

4. The memory controller of claim 3 , wherein, for the determining of whether to change the order of the first command, the command scheduler is configured to maintain the order of the first command in response to the type of the first command indicating the PIM memory.

5. The memory controller of claim 3 , wherein, for the determining of whether to change the order of the first command, the command scheduler is configured to change the order of the first command in response to the type of the first command indicating the general memory.

6. The memory controller of claim 3 , wherein

the memory request comprises a field indicating the address,

the field comprises an area separating bit that separates an address of the general memory and an address of the PIM memory, and

for the setting of the type of the first command, the request arbiter is configured to set the type of the first command based on the area separating bit.

7. A memory control method comprising:

by a first buffer, receiving a memory request from a host and storing therein the received memory request;

by a command generator, generating a first command corresponding to the memory request, and setting a type of the first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory or a general memory;

by a second buffer, storing therein a plurality of commands comprising the first command; and

by a command scheduler, maintaining an order of the first command among commands corresponding to the PIM memory stored in the second buffer in response to the type of the first command indicating the PIM memory and changing the order of the first command among the commands corresponding to the general memory in response to the type indicating the general memory.

8. A memory control method comprising:

by a first buffer, receiving a memory request from a host and storing therein the received memory request;

by a request arbiter, setting a type of a first command indicating whether an address comprised in the memory request corresponds to a processing in memory (PIM) memory or a general memory, maintaining an order of the memory request among memory requests corresponding to the PIM memory to be transferred to a command generator in response to the type of the first command indicating the PIM memory and changing the order of the memory request among the memory requests corresponding to the general memory in response to the type indicating the general memory;

by the command generator, generating the first command corresponding to the memory request and the type of the first command based on the order of the memory request;

by a second buffer, storing therein a plurality of commands comprising the first command; and

by a command scheduler, determining whether to change an order of the first command stored in the second buffer based on the type of the first command.

9. The memory control method of claim 8 , wherein the determining of whether to change the order of the first command comprises:

in response to the type of the first command indicating the PIM memory, maintaining the order of the first command.

10. The memory control method of claim 8 , wherein the determining of whether to change the order of the first command comprises:

in response to the type of the first command indicating the general memory, changing the order of the first command.

11. The memory control method of claim 8 , wherein

the memory request comprises a field indicating the address,

the field comprises an area separating bit that separates an address of the general memory and an address of the PIM memory, and

the setting of the type of the first command comprises setting the type of the first command based on the area separating bit.

12. A memory controller comprising:

a command generator configured to set a type of a command based on an area separating bit of an address in a stored memory request, the type indicating whether the address corresponds to a processing in memory (PIM) memory or a general memory;

a command scheduler configured to:

maintain an order of the command among commands corresponding to the PIM memory stored in a buffer, in response to the type of the command set by the command generator indicating the PIM memory; and

change the order of the first command among the commands corresponding to the general memory, in response to the type indicating the general memory.

13. The memory controller of claim 12 , wherein

the area separating bit corresponds to a value range, and

for the setting of the type of the command, the command generator is configured to:

set the type of the command indicating the address corresponds to the PIM memory, in response to a value of a field of the address being greater than the value range; and

set the type of the command indicating the address corresponds to the general memory, in response to the value of the field being within the value range.

14. The memory controller of claim 12 , wherein the command scheduler is configured to change an order of one or more other commands stored in the buffer, in response to the type of the command indicating the PIM memory.

15. The memory controller of claim 12 , wherein the memory controller is configured to access a memory based on the order of the command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2021
From: YOON, HOSANG; LEE, SEUNGWON
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 057577/0931 →
Priority Claims (2)
KR 10-2021-0017653 · Feb 8, 2021 · national
KR 10-2021-0058628 · May 6, 2021 · national
Continuity (1)
Related Publication 20220253248A1 · Aug 11, 2022
Cited By (2)
US 12,197,774 US 12,204,757