Insulated gate semiconductor device
An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type provided at an upper part of the injection control region; a base contact region of the second conductivity-type provided at an upper part of the injection control region; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; and a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches, wherein the lower buried region is separated from each other via the carrier transport layer between the trenches.
1 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type provided on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively provided at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively provided at an upper part of the injection control region;
trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure provided inside the respective trenches;
an upper buried region of the second conductivity-type provided inside the carrier transport layer to be in contact with a bottom surface of the injection control region; and
a lower buried region of the second conductivity-type provided inside the carrier transport layer to be in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches,
wherein
the lower buried region is disposed at positions separated from each other via the carrier transport layer between the trenches adjacent to each other, and the bottom surface of the upper buried region is in contact with the carrier transport layer,
the lower buried region includes:
a first lower buried region in contact with a bottom surface of a first trench of the adjacent trenches; and
a second lower buried region in contact with a bottom surface of a second trench of the adjacent trenches, and
an edge of the first lower buried region on the second trench side and an edge of the second lower buried region on the first trench side are in contact with the bottom surface of the upper buried region.
2 . The insulated gate semiconductor device of claim 1 , wherein the lower buried region has corner parts defined by side surfaces and a bottom surface at edges separated to be opposed to each other.
3 . The insulated gate semiconductor device of claim 1 , wherein the base contact region is provided in a middle between the trenches adjacent to each other.
4 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the base contact region are separated from the trenches adjacent to each other.
5 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the upper buried region are separated from the trenches adjacent to each other.
6 . The insulated gate semiconductor device of claim 1 , wherein the upper buried region has a narrower width than the base contact region.
7 . The insulated gate semiconductor device of claim 1 , wherein the upper buried region has a width that is greater than a gap between the respective positions of the lower buried region separated from each other.
8 . The insulated gate semiconductor device of claim 1 , wherein the base contact region, the injection control region, the upper buried region, and the lower buried region straightly overlap with each other in a depth direction of the trenches.
9 . The insulated gate semiconductor device of claim 1 , wherein the carrier transport layer includes
a drift layer of the first conductivity-type, and
a current spreading layer of the first conductivity-type provided on the drift layer.
10 . The insulated gate semiconductor device of claim 1 , wherein:
the trenches adjacent to each other extend parallel to each other in a planar pattern; and
the lower buried region includes
stripe parts extending in a direction parallel to the trenches, and
projecting parts connected to the stripe parts and projecting in a direction perpendicular to the extending direction of the stripe parts.
11 . The insulated gate semiconductor device of claim 1 , wherein:
the trenches adjacent to each other extend parallel to each other in a planar pattern; and
the lower buried region is provided to have stripe parts extending parallel to the trenches, and includes a part that is in contact with the upper buried region and has a greater width than a part not in contact with the upper buried region.
12 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the base contact region are in contact with the respective trenches adjacent to each other.
13 . The insulated gate semiconductor device of claim 1 , wherein side surfaces on both sides of the upper buried region are in contact with the respective trenches adjacent to each other.
14 . The insulated gate semiconductor device of claim 1 , further comprising a high-concentration region of the first conductivity-type provided on bottom surfaces of end parts of the positions of the lower buried region opposed to each other.
15 . The insulated gate semiconductor device of claim 1 , wherein the base contact region and the upper buried region are provided at positions shifted from each other in a depth direction of the trenches.
16 . The insulated gate semiconductor device of claim 1 , wherein:
the trenches adjacent to each other extend parallel to each other in a planar pattern; and
the upper buried region has a stripe-shaped planar pattern extending in a direction in which the trenches extend.
17 . The insulated gate semiconductor device of claim 16 , wherein the base contact region has a stripe-shaped planar pattern extending in the extending direction of the trenches.
18 . The insulated gate semiconductor device of claim 1 , wherein:
the trenches adjacent to each other extend parallel to each other in a planar pattern;
the base contact region and the upper buried region are located at positions overlapping with each other intermittently in a direction in which the trenches extend; and
a gap between the positions at which the base contact region and the upper buried region are located differs among a plurality of active areas.
19 . An insulated gate semiconductor device comprising:
a carrier transport layer of a first conductivity-type;
an injection control region of a second conductivity-type provided on a top surface of the carrier transport layer;
a carrier supply region of the first conductivity-type selectively provided at an upper part of the injection control region;
a base contact region of the second conductivity-type selectively provided at an upper part of the injection control region;
trenches penetrating the injection control region to reach the carrier transport layer;
an insulated gate structure provided inside the respective trenches;
an upper buried region of the second conductivity-type provided inside the carrier transport layer to be in contact with a bottom surface of the injection control region; and
a lower buried region of the second conductivity-type provided inside the carrier transport layer to be in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches,
wherein the lower buried region is provided as a first lower buried region and a second lower buried region spaced apart from each other via the carrier transport layer between adjacent trenches, a portion of the carrier transport layer is interposed between the first lower buried region and the second lower buried region and extends from the first lower buried region to the second lower buried region, and the upper buried region is provided over and covers the entire portion of the carrier transport layer.