IP Library Granted Patent US 12,727,460
Granted Patent B2
US 12,727,460 · App. 18/072,569 · Granted Sep 1, 2026

Integrated circuit structure with recessed trench contact and deep boundary via

Inventors: Tao Chu (Portland, OR); Guowei Xu (Portland, OR); Feng Zhang (Hillsboro, OR); Chiao-Ti Huang (Portland, OR); Minwoo Jang (Portland, OR)
Assignee: Intel Corporation
H10W20/20H10D30/6729H10D30/6757H10D62/121H10D84/834
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Quick Facts
Patent No.
US 12,727,460
App. No.
18/072,569
Granted
Sep 1, 2026
Kind
B2
Abstract

Integrated circuit structures having recessed trench contacts and deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extends over a plurality of source or drain structures, where a first one of the plurality of trench contacts has a recess therein. A backside metal routing layer is extending beneath the plurality of gate lines and beneath the plurality of trench contacts. A conductive structure couples the backside metal routing layer to a second one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Claims (46)

1 . An integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;

a plurality of trench contacts extending over a plurality of source or drain structures, wherein a first one of the plurality of trench contacts has a recess in metal of the trench contact;

a backside metal routing layer extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

2 . The integrated circuit structure of claim 1 , wherein the backside metal routing layer is a backside power delivery line.

3 . The integrated circuit structure of claim 1 , wherein the conductive structure is a recessed deep boundary via structure.

4 . The integrated circuit structure of claim 1 , wherein the pillar portion of the conductive structure extends between a pair of N-type source or drain structures of plurality of source or drain structures or extends between a pair of P-type source or drain structures of plurality of source or drain structures.

5 . The integrated circuit structure of claim 1 , further comprising a dielectric liner along sides of the pillar portion and the line portion of the conductive structure.

6 . An integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor fin structures;

a plurality of trench contacts extending over a plurality of source or drain structures, wherein a first one of the plurality of trench contacts has a recess in metal of the trench contact;

a backside metal routing layer extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

7 . The integrated circuit structure of claim 6 , wherein the backside metal routing layer is a backside power delivery line.

8 . The integrated circuit structure of claim 6 , wherein the conductive structure is a recessed deep boundary via structure.

9 . The integrated circuit structure of claim 6 , wherein the pillar portion of the conductive structure extends between a pair of N-type source or drain structures of plurality of source or drain structures or extends between a pair of P-type source or drain structures of plurality of source or drain structures.

10 . The integrated circuit structure of claim 6 , further comprising a dielectric liner along sides of the pillar portion and the line portion of the conductive structure.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;

a plurality of trench contacts extending over a plurality of source or drain structures, wherein a first one of the plurality of trench contacts has a recess in metal of the trench contact;

a backside metal routing layer extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:

a camera coupled to the board.

15 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a plurality of gate lines extending over a plurality of semiconductor fin structures;

a plurality of trench contacts extending over a plurality of source or drain structures, wherein a first one of the plurality of trench contacts has a recess in metal of the trench contact;

a backside metal routing layer extending beneath the plurality of gate lines and beneath the plurality of trench contacts; and

a conductive structure coupling the backside metal routing layer to a second one of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the second one of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , further comprising:

a camera coupled to the board.

20 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2023
From: CHU, TAO; XU, GUOWEI; ZHANG, FENG; HUANG, CHIAO-TI; JANG, MINWOO
To: INTEL CORPORATION
Reel/Frame 063578/0600 →
Continuity (1)
Related Publication 20240178101A1 · May 30, 2024
References Cited (2)
US 20230215767A1 · Xie · 2023 [cited by examiner]
US 20230345691A1 · Xie · 2023 [cited by examiner]