Circuit design modification based on timing tradeoff
Various embodiments provide for modifying a circuit design based on timing tradeoff, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a return on investment (ROI) concept to determine one or more thresholds for how much area or power of a circuit design should be available for use (e.g., sacrificed) in order to obtain an improvement in slack by a given transformation.
1 . A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
accessing data that describes a netlist for a circuit design;
determining a select region of the circuit design for a transformation configured to alter a logic of the select region, the select region corresponding to a subset of the netlist;
determining, from a class of transforms, a set of transforms for the select region; and
for an individual transform in the set of transforms:
determining, based on a timing-aware tradeoff model, whether application of the individual transform on the select region is acceptable, the timing-aware tradeoff model being configured to evaluate transforms based on a constrained timing arc of the select region; and
in response to determining that the application of the individual transform on the region is acceptable, committing the individual transform to the select region to generate an altered region that replaces the select region in the circuit design.
2 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that improve slack in the select region when the constrained timing arc is determined to be high based on a threshold value.
3 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that lower power consumption by the select region when the constrained timing arc is determined to be low based on a threshold value.
4 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that reduce area of the circuit design occupied by the select region when the constrained timing arc is determined to be low based on a threshold value.
5 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
applying a minimum ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic.
6 . The non-transitory computer-readable medium of claim 5 , wherein the minimum ratio is determined based on a sigmoid curve that compares a slack-dependent threshold against a negative slack.
7 . The non-transitory computer-readable medium of claim 5 , wherein the minimum ratio is determined based on a sigmoid transition function defined as:
f
(
s
)
=
0
.
5
[
1
-
tanh
(
s
-
s
min
s
width
)
]
,
where s min represents a minimum slack transition value, and where s width represents a slack transition width.
8 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
evaluating a gain in timing optimization using a following formula:
(
R
min
-
R
max
)
*
f
(
s
)
+
R
max
>
Δ
s
Cost
,
where f(s) is a function defining a sigmoid curve for determining a ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic, where R min is a minimum ratio, where R max is a maximum ratio, where Cost represents an area cost or a power cost, and where Δs represents a difference in slack after the individual transform and before the individual transform.
9 . The non-transitory computer-readable medium of claim 1 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
evaluating a gain in power optimization or an area optimization using a following formula:
(
R
min
-
R
max
)
+
R
max
*
f
(
s
)
>
Gain
-
Δ
s
,
where f(s) is a function defining a sigmoid curve for determining a ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic, where R min is a minimum ratio, where R max is a maximum ratio, where Gain represents an area gain or a power gain, and where Δs represents a difference in slack after the individual transform and before the individual transform.
10 . A device comprising:
a memory storing instructions; and
a hardware processor communicatively coupled to the memory and configured by the instructions to perform operations comprising:
accessing data that describes a netlist for a circuit design;
determining a select region of the circuit design for a transformation configured to alter a logic of the select region, the select region corresponding to a subset of the netlist;
determining, from a class of transforms, a set of transforms for the select region; and
for an individual transform in the set of transforms:
determining, based on a timing-aware tradeoff model, whether application of the individual transform on the select region is acceptable, the timing-aware tradeoff model being configured to evaluate transforms based on a constrained timing arc of the select region; and
in response to determining that the application of the individual transform on the region is acceptable, committing the individual transform to the select region to generate an altered region that replaces the select region in the circuit design.
11 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that improve slack in the select region when the constrained timing arc is determined to be high based on a threshold value.
12 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that lower power consumption by the select region when the constrained timing arc is determined to be low based on a threshold value.
13 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
prioritizing transforms that reduce area of the circuit design occupied by the select region when the constrained timing arc is determined to be low based on a threshold value.
14 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
applying a minimum ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic.
15 . The device of claim 14 , wherein the minimum ratio is determined based on a sigmoid curve that compares a slack-dependent threshold against a negative slack.
16 . The device of claim 14 , wherein the minimum ratio is determined based on a sigmoid transition function defined as:
f
(
s
)
=
0
.
5
[
1
-
tanh
(
s
-
s
min
s
width
)
]
,
where s min represents a minimum slack transition value, and where s width represents a slack transition width.
17 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
evaluating a gain in timing optimization using a following formula:
(
R
min
-
R
max
)
*
f
(
s
)
+
R
max
>
Δ
s
Cost
,
where f(s) is a function defining a sigmoid curve for determining a ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic, where R min is a minimum ratio, where R max is a maximum ratio, where Cost represents an area cost or a power cost, and where Δs represents a difference in slack after the individual transform and before the individual transform.
18 . The device of claim 10 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by:
evaluating a gain in power optimization or an area optimization using a following formula:
(
R
min
-
R
max
)
+
R
max
*
f
(
s
)
>
Gain
-
Δ
s
,
where f(s) is a function defining a sigmoid curve for determining a ratio of an improvement of the circuit design by the individual transform in a first design characteristic for a degradation of the circuit design in a second design characteristic, where R min is a minimum ratio, where R max is a maximum ratio, where Gain represents an area gain or a power gain, and where Δs represents a difference in slack after the individual transform and before the individual transform.
19 . A method comprising:
accessing, by a hardware processor, data that describes a netlist for a circuit design;
determining, by the hardware processor, a select region of the circuit design for a transformation configured to alter a logic of the select region, the select region corresponding to a subset of the netlist;
determining, by the hardware processor and from a class of transforms, a set of transforms for the select region; and
for an individual transform in the set of transforms:
determining, by the hardware processor and based on a timing-aware tradeoff model, whether application of the individual transform on the select region is acceptable, the timing-aware tradeoff model being configured to evaluate transforms based on a constrained timing arc of the select region; and
in response to determining that the application of the individual transform on the region is acceptable, committing, by the hardware processor, the individual transform to the select region to generate an altered region that replaces the select region in the circuit design.
20 . The method of claim 19 , wherein the timing-aware tradeoff model is configured to evaluate transforms based on the constrained timing arc of the select region by performing at least one of:
prioritizing transforms that improve slack in the select region when the constrained timing arc is determined to be high based on a threshold value;
prioritizing transforms that lower power consumption by the select region when the constrained timing arc is determined to be low based on the threshold value; or
prioritizing transforms that reduce area of the circuit design occupied by the select region when the constrained timing arc is determined to be low based on the threshold value.