Reinforcement learning-based adjustment of digital circuits

1. A method of adjusting a digital circuit design, the method comprising:

selecting a first path in the digital circuit design, the first path comprising a plurality of gates;

generating a k-hop neighborhood graph of the first path, where k is a positive integer;

encoding the k-hop neighborhood graph into a state vector;

applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates; and

changing the first gate based on the adjustment.

2. The method of claim 1 , further comprising:

performing a static timing analysis on the digital circuit design after changing the first gate; and

updating the machine learning model based on results of the static timing analysis.

3. The method of claim 1 , wherein selecting the first path comprises performing a static timing analysis to identify a plurality of paths.

4. The method of claim 3 , wherein selecting the first path comprises selecting the first path from the plurality of paths based on a slack of the first path.

5. The method of claim 1 , further comprising applying the machine learning model to determine a second adjustment on the first gate if an objective function of the digital circuit design does not converge.

6. The method of claim 1 , further comprising applying the machine learning model to determine a second adjustment on a second gate of a second path in the digital circuit design after changing the first gate.

7. The method of claim 1 , wherein the adjustment is to one or more of gate sizing, buffering, logic restructuring, sequencing, clock-tree skewing, placement, and routing.

8. An apparatus for adjusting a digital circuit design, the apparatus comprising:

a memory; and

a hardware processor communicatively coupled to the memory, the hardware processor configured to:

generate a k-hop neighborhood graph for a first gate in the digital circuit design, wherein the k-hop neighborhood graph comprises a plurality of nodes representing a plurality of neighbors of the first gate in the digital circuit design;

encode the k-hop neighborhood graph into a state vector comprising a numerical representation of the first gate and the plurality of neighbors;

apply a machine learning model to the state vector to determine, based on a graph neural network, an adjustment to be made to the first gate; and

change the first gate based on the adjustment.

9. The apparatus of claim 8 , wherein the hardware processor is further configured to:

perform a static timing analysis on the digital circuit design after changing the first gate; and

update the machine learning model based on results of the static timing analysis.

10. The apparatus of claim 8 , wherein the hardware processor is further configured to select a path comprising the first gate by performing a static timing analysis to identify the path.

11. The apparatus of claim 10 , wherein selecting the path comprises selecting the path from a plurality of paths based on a slack of the path.

12. The apparatus of claim 8 , wherein the hardware processor is further configured to apply the machine learning model to determine a second adjustment on the first gate if an objective function of the digital circuit design does not converge.

13. The apparatus of claim 8 , wherein the hardware processor is further configured to apply the machine learning model to determine a second adjustment on a second gate in the digital circuit design after changing the first gate.

14. The apparatus of claim 8 , wherein the adjustment is to one or more of gate sizing, buffering, logic restructuring, sequencing, clock-tree skewing, placement, and routing.

15. A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform an operation for adjusting a digital circuit design, the operation comprising:

generating a plurality of k-hop neighborhood graphs for a plurality of gates in the digital circuit design;

encoding the plurality of k-hop neighborhood graphs into a plurality of state vectors;

applying a machine learning model to the plurality of state vectors to determine a plurality of adjustments to be made to the plurality of gates that improve a power, performance, and area (PPA) of the digital circuit design even though an adjustment of the plurality of adjustments worsens the PPA of the digital circuit design; and

changing the plurality of gates based on the plurality of adjustments.

16. The non-transitory computer readable medium of claim 15 , wherein the operation further comprises:

performing a static timing analysis on the digital circuit design after changing the plurality of gates; and

updating the machine learning model based on results of the static timing analysis.

17. The non-transitory computer readable medium of claim 15 , wherein the operation further comprises selecting a path comprising the plurality of gates by performing a static timing analysis to identify the path.

18. The non-transitory computer readable medium of claim 17 , wherein selecting the path comprises selecting the path from a plurality of paths based on a slack of the path.

19. The non-transitory computer readable medium of claim 15 , wherein the operation further comprises applying the machine learning model to determine an adjustment on a gate of the plurality of gates if an objective function of the digital circuit design does not converge.

20. The non-transitory computer readable medium of claim 15 , wherein the operation further comprises applying the machine learning model to determine a second adjustment on a second gate in the digital circuit design after changing a first gate of the plurality of gates.