Granted Patent B2

US 12,463,132 · App. 18/078,454 · Granted Nov 4, 2025

Inventors: Ruilong Xie (Niskayuna, NY); Koichi Motoyama (Clifton Park, NY); Nicholas Anthony Lanzillo (Wynantskill, NY); Oleg Gluschenkov (Tannersville, NY)

Assignee: International Business Machines Corporation

H01L23/5226H01L21/76802H01L21/76831H01L21/76877H01L23/5286

Abstract

Claims (36)

1 . A semiconductor structure, comprising:

a first metallization layer comprising a first plurality of metal containing lines; and

a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines;

wherein the first metallization layer is a first backside metallization layer;

wherein a first group of the second plurality of metal containing lines is disposed within the first metallization layer; and

wherein the first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

2 . The semiconductor structure according to claim 1 , wherein the second metallization layer is a second backside metallization layer.

3 . The semiconductor structure according to claim 1 , wherein the second plurality of metal containing lines are oriented perpendicular to the first plurality of metal containing lines.

4 . The semiconductor structure according to claim 1 , wherein the second plurality of metal containing lines further comprises a second group of the second plurality of metal containing lines, wherein at least one of the metal containing lines of the second group is disposed on at least one of the first plurality of metal containing lines.

5 . The semiconductor structure according to claim 1 , wherein the first group of the second plurality of metal containing lines comprises ground Vss rails.

6 . The semiconductor structure according to claim 5 , wherein the second plurality of metal containing lines further comprises a second group comprising power Vdd rails.

7 . The semiconductor structure according to claim 1 , wherein the dielectric barrier layer comprises a high-k dielectric material.

8 . The semiconductor structure according to claim 1 , wherein the first metallization layer and the second metallization layer are part of a backside power delivery network.

9 . The semiconductor structure according to claim 1 , wherein the second plurality of metal containing lines further comprises a second group of the plurality of metal containing lines in direct contact with a first group of the first plurality of metal containing lines.

10 . A semiconductor structure, comprising:

a first metallization layer comprising a first plurality of metal containing lines in a first orientation; and

a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines in a second orientation;

wherein the second plurality of metal containing lines comprises a first group of the second plurality of metal containing lines and a second group of the second plurality of metal containing lines;

wherein the first group of the second plurality of metal containing lines is disposed within the first metallization layer and isolated from the first metallization layer by a dielectric barrier layer; and

wherein at least one of the metal containing lines of the second group of the second plurality of metal containing lines is directly connected to at least one of the first plurality of metal containing lines.

11 . The semiconductor structure according to claim 10 , wherein the first metallization layer is a first backside metallization layer and the second metallization layer is a second backside metallization layer.

12 . The semiconductor structure according to claim 10 , wherein the second plurality of metal containing lines are oriented perpendicular to the first plurality of metal containing lines.

13 . The semiconductor structure according to claim 10 , wherein the first group of the second plurality of metal containing lines comprises ground Vss rails.

14 . The semiconductor structure according to claim 13 , wherein the second group of the second plurality of metal containing lines comprises power Vdd rails.

15 . The semiconductor structure according to claim 10 , wherein the dielectric barrier layer comprises a high-k dielectric material.

16 . The semiconductor structure according to claim 10 , wherein the first metallization layer and the second metallization layer are part of a backside power delivery network.

17 . The semiconductor structure according to claim 10 , wherein the first plurality of metal containing lines comprises a first group comprising ground Vss rails and a second group comprising power Vdd rails.

18 . An integrated circuit, comprising:

one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:

a first metallization layer comprising a first plurality of metal containing lines; and

a second metallization layer located above the first metallization layer, wherein the second metallization layer comprises a second plurality of metal containing lines;

wherein the first metallization layer is a first backside metallization layer;

wherein a first group of the second plurality of metal containing lines is disposed within the first metallization layer; and

wherein the first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

19 . The integrated circuit according to claim 18 , wherein the second metallization layer is a second backside metallization layer; and wherein the second plurality of metal containing lines are oriented perpendicular to the first plurality of metal containing lines.

20 . The integrated circuit according to claim 18 , wherein the first metallization layer and the second metallization layer are part of a backside power delivery network.

Assignments (1)

Continuity (1)

References Cited (26)