Via-free interconnect structure with self-aligned metal line interconnections

1. A semiconductor device, comprising:

a substrate;

a first conductive line disposed over the substrate, wherein the first conductive line is located in a first interconnect layer and extends along a first direction;

a second conductive line and a third conductive line each extending along a second direction different from the first direction, wherein the second and third conductive lines are located in a second interconnect layer different from the first interconnect layer, and wherein the second and third conductive lines are separated by a gap that is located over or below the first conductive line;

a fourth conductive line electrically coupling the second and third conductive lines together, the fourth conductive line being located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer;

a fifth conductive line being located in the first interconnect layer; and

a sixth conductive line being located in the second interconnect layer;

wherein the fifth conductive line and the sixth conductive line are in direct physical contact.

2. The semiconductor device of claim 1 , wherein the fourth conductive line extends along the second direction.

3. The semiconductor device of claim 1 , wherein the first direction is perpendicular to the second direction.

4. The semiconductor device of claim 1 , wherein the fourth conductive line is disposed over the gap between the second and third conductive lines.

5. The semiconductor device of claim 1 , wherein at least one of the first, second, and third interconnect layers is free of vias.

6. The semiconductor device of claim 1 , wherein the gap between the second and third conductive lines is filled by a dielectric component.

7. A semiconductor interconnect structure, comprising:

a first metal layer formed over a substrate, the first metal layer containing a first metal line that is oriented in a first direction;

a second metal layer formed over the substrate, the second metal layer being different from the first metal layer and containing a second metal line, a third metal line, and a dielectric component separating the second and third metal lines, the second and third metal lines being oriented in a second direction different from the first direction;

a third metal layer formed over the substrate, the third metal layer being different from the first metal layer and the second metal layer, the third metal layer containing a fourth metal line being located over or below the dielectric component and bridging the second and third metal lines;

a fourth metal layer that is formed between the second metal layer and the third metal layer, and wherein the fourth metal layer contains:

a fifth metal line that is formed between the second metal line and the fourth metal line; and

a sixth metal line that is formed between the third metal line and the fourth metal line.

8. The semiconductor device of claim 7 , wherein:

the fourth metal line is oriented in the second direction; and

the first direction is perpendicular to the second direction.

9. The semiconductor device of claim 7 , wherein the fifth and sixth metal lines are each oriented in the first direction.

10. The semiconductor device of claim 7 , wherein at least one of the first, second, and third metal layers is free of electrical vias.

11. A semiconductor device, comprising:

a substrate;

a first conductive line disposed over the substrate, wherein the first conductive line is located in a first interconnect layer and extends along a first direction;

a second conductive line and a third conductive line each extending along a second direction different from the first direction, wherein the second and third conductive lines are located in a second interconnect layer different from the first interconnect layer, and wherein the second and third conductive lines are separated by a gap that is located over or below the first conductive line; and

a fourth conductive line electrically coupling the second and third conductive lines together, the fourth conductive line being located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer;

wherein at least one of the first, second, and third interconnect layers is free of vias.

12. The semiconductor device of claim 11 , wherein the second, third and fourth conductive lines each consist of a single layer of conductive material.

13. The semiconductor device of claim 11 , wherein:

the first interconnect layer further contains a fifth conductive line; and

the second interconnect layer further contains a sixth conductive line that is in direct physical contact with the fifth conductive line.

14. The semiconductor device of claim 11 , further comprising:

a fourth interconnect layer that is formed between the second interconnect layer and the third interconnect layer, and wherein the fourth interconnect layer contains:

a fifth conductive line that is formed between the second conductive line and the fourth conductive line; and

a sixth conductive line that is formed between the third conductive line and the fourth conductive line.

15. The semiconductor device of claim 14 , wherein the fifth and sixth conductive lines are each oriented in the first direction.

16. The semiconductor device of claim 11 , wherein the fourth conductive line is oriented in the second direction.

17. The semiconductor device of claim 11 , wherein the first direction is perpendicular to the second direction.

18. The semiconductor device of claim 11 , wherein the fourth conductive line is located over or below the gap separating the second and third conductive lines.

19. The semiconductor device of claim 11 , wherein the gap separating the second and third conductive lines is filled by a dielectric component.