Fine-grained dirty page tracking of IOMMU second-stage large pages
An example of an apparatus may include memory and an input/output (IO) bus, where an address space of the memory and the IO bus is at least partially organized as a plurality of large pages, and where a large page is organized as two or more sub-pages. In some examples, the apparatus further includes circuitry coupled to the memory and the IO bus to map an IO address to a physical address, and track a modification to a large page at a granularity that corresponds to a size of a subset of the large page. Other embodiments are disclosed and claimed.
1 . An apparatus, comprising:
memory and an input/output (IO) bus, wherein an address space of the memory and the IO bus is at least partially organized as a plurality of large pages, and wherein a large page is organized as two or more sub-pages; and
an input/output memory management unit (IOMMU) coupled to the memory and the IO bus, the IOMMU comprising circuitry to:
map an IO address to a physical address; and
track a modification to the large page at a granularity that corresponds to a size of a subset of the large page.
2 . The apparatus of claim 1 , wherein the circuitry is further to:
selectively track the modification to the large page at any of multiple granularities based on a configuration setting, the multiple granularities comprising:
a first granularity that corresponds to the size of the subset of the large page; and
a second granularity that corresponds to the size of the large page.
3 . The apparatus of claim 2 , wherein the circuitry is further to:
determine the configuration setting based on a field of a register.
4 . The apparatus of claim 1 , wherein the circuitry is further to:
maintain a page table to map the IO address to the physical address; and
maintain a shadow page table to track the modification to the large page at the granularity that corresponds to the size of the subset of the large page.
5 . The apparatus of claim 4 , wherein the shadow page table is adjacent and physically contiguous to the page table.
6 . The apparatus of claim 4 , wherein the circuitry is further to:
set a value of a field in a page table entry of the shadow page table to indicate a modification to a sub-page of the large page.
7 . The apparatus of claim 6 , wherein the field in the page table entry corresponds to a range of two or more sub-pages of the large page, wherein a size of the range corresponds to the size of the subset of the large page.
8 . The apparatus of claim 4 , wherein the circuitry is further to:
maintain a shadow pointer table with an entry to point to the shadow page table.
9 . The apparatus of claim 8 , wherein the shadow pointer table is adjacent and physically contiguous to the page table.
10 . An apparatus, comprising:
memory; and
an input/output memory management unit (IOMMU) coupled to the memory, the IOMMU including circuitry to:
manage access from input/output (IO) devices to the memory at a page level that includes at a higher-level page and a lower-level page, wherein a higher-level page includes a plurality of lower-level pages, and
selectively track higher-level dirty pages at any of multiple granularities comprising:
a first granularity that corresponds to a first size of a higher-level page; and
a second granularity that corresponds to a second size of a subset of the higher-level page.
11 . The apparatus of claim 10 , further comprising:
a register to store an indication of whether the circuitry is to track higher-level dirty pages at the first granularity or the second granularity.
12 . The apparatus of claim 11 , wherein the circuitry is further to:
determine if an IO device modifies a higher-level page; and
set a dirty bit in a shadow higher-level page table entry that corresponds to a modified subset of the higher-level page if the register stores an indication that the circuitry is to track higher-level dirty pages at the second granularity.
13 . The apparatus of claim 11 , wherein the memory is to store a table with an indication of whether the first size of the higher-level page corresponds to a first large page size or a second large page size.
14 . The apparatus of claim 13 , wherein, if the register stores an indication that the circuitry is to track higher-level dirty pages at the second granularity, the circuitry is further to:
utilize a shadow higher-level page structure that is adjacent to a higher-level page directory to store dirty bits that correspond to modified subsets of a higher-level page, if the table stores an indication that the first size of the higher-level page corresponds to the first large page size.
15 . The apparatus of claim 13 , wherein, if the register stores an indication that the circuitry is to track higher-level dirty pages at the second granularity, the circuitry is further to:
utilize a first shadow higher-level page structure that is adjacent to a higher-level page directory to store pointers to respective second shadow higher-level page structures that store dirty bits that correspond to modified subsets of a higher-level page, if the table stores an indication that the first size of the higher-level page corresponds to the second large page size.
16 . A system, comprising:
a processor;
memory;
a memory management unit (MMU) coupled between the processor and the memory; and
an input/output (IO) MMU (IOMMU) coupled to the memory to manage access to the memory from one or more IO devices and to selectively track dirty large pages at any of multiple granularities comprising:
a first granularity that corresponds to a first size of a large page; and
a second granularity that corresponds to a second size of a subset of the large page, wherein the large page includes two or more sub-pages.
17 . The system of claim 16 , wherein the memory is to store a page table with an indication of whether the first size of the large page corresponds to a first large page size or a second large page size.
18 . The system of claim 16 , further comprising:
a configuration register to store a global indication of one or more granularities to be tracked for the dirty large pages.
19 . The system of claim 18 , further comprising non-transitory instructions that when executed by the processor cause the processor to determine if the configuration register stores an indication that the IOMMU is to track dirty large pages at the second granularity and, if so determined, to:
create a first set of page structures to be utilized by the IOMMU to manage the access to the memory from the one or more IO devices; and
create a second set of shadow page structures to be utilized by the IOMMU to track dirty subsets of the dirty large pages.
20 . The system of claim 19 , wherein the IOMMU is further to:
set a dirty bit in a shadow page table entry of the second set of shadow page structures that corresponds to a modified subset of a modified large page.
21 . The system of claim 19 , further comprising non-transitory instructions that when executed by the processor cause the processor to:
migrate only subsets of large pages indicated as dirty by the second set of shadow page structures, in response to a migration request.