Method and system for implementing multi-stage translation of virtual addresses
A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.
1. A method comprising:
receiving, at a first memory management unit, a memory request including a virtual address in a first address space;
translating the virtual address to generate a second virtual address in a second address space using a first page table including entries configured for a first page size, wherein the first page table entries include a first attribute that is consistent for pages of the first page size including a first physical page in a memory; and
transmitting a modified memory request including the second virtual address to a second memory management unit,
wherein the second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space using a second page table including entries configured for a second page size that is different compared with the first page size, wherein the second page table entries include a second attribute that is consistent for pages of the second page size and varies for pages of the first page size including the first physical page,
wherein the physical address is associated with a location in the first physical page, and
wherein the first memory management unit and the second memory management unit are implemented in hardware.
2. The method of claim 1 , wherein the first address space comprises an application address space.
3. The method of claim 1 , wherein the first memory management unit includes a translation lookaside buffer (TLB).
4. The method of claim 3 , further comprising:
determining that the TLB does not include a copy of a page table entry associated with the virtual address;
generating a memory request to read the page table entry associated with the virtual address from the memory;
receiving a response for the memory request including data representing the copy of the page table entry associated with the virtual address; and
storing the data representing the copy of the page table entry associated with the virtual address in a slot of the TLB.
5. The method of claim 4 , wherein the data representing the copy of the page table entry associated with the virtual address includes the first attribute that is associated with a page of memory corresponding to the page table entry associated with the virtual address.
6. The method of claim 5 , wherein the second memory management unit includes a second TLB, and wherein the second memory management unit, in response to receiving the modified memory request, is further configured to:
determine that the second TLB does not include a copy of a page table entry associated with the second virtual address;
generate a second memory request to read the page table entry associated with the second virtual address from the memory;
receive a response for the memory request including data representing the copy of the page table entry associated with the second virtual address; and
store the data representing the copy of the page table entry associated with the second virtual address in a slot of the second TLB.
7. The method of claim 1 , wherein the first attribute comprises a compression format for data stored in a first page of memory.
8. The method of claim 1 , wherein the first attribute comprises an address that points to compression state information for a first page of memory.
9. The method of claim 1 , wherein the entries in the first page table each include a bit indicating whether the first memory management unit is configured to translate the virtual address in the first address space directly to the physical address in the third address space and the second memory management unit is disabled for the virtual address.
10. The method of claim 1 , wherein the memory request including the virtual address in the first address space is generated by a third memory management unit in response to receiving a memory request including a third virtual address in a third address space.
11. The method of claim 10 , wherein the third address space comprises an application address space, the first address space comprises a first intermediate address space, and the second address space comprises a second intermediate address space.
12. The method of claim 1 , wherein the first page size is larger than the second page size and the first attribute is associated with the first page size and is not associated with the second page size.
13. The method of claim 1 , wherein a size of the virtual address and a size of the physical address are not equal.
14. The method of claim 1 , wherein the first attribute is not stored in the second page table and the second attribute is not stored in the first page table.
15. A system comprising: a first memory management unit configured to:
receive a memory request including a virtual address in a first address space,
translate the virtual address to generate a second virtual address in a second address space using a first page table including entries configured for a first page size, wherein the first page table entries include a first attribute that is consistent for pages of the first page size including a first physical page in a memory, and
transmit a modified memory request including the second virtual address to a second memory management unit; and the second memory management unit configured to:
translate the second virtual address to generate a physical address in a third address space using a second page table including entries configured for a second page size that is different compared with the first page size, wherein the second page table entries include and a second attribute that is consistent for pages of the second page size and varies for pages of the first page size including the first physical page,
wherein the physical address is associated with a location in the first physical page,
wherein the first memory management unit and the second memory management unit are implemented in hardware.
16. The system of claim 15 , wherein the first memory management unit includes a translation lookaside buffer (TLB), the first memory management unit further configured to:
determine that the TLB does not include a copy of a page table entry associated with the virtual address;
generate a memory request to read the page table entry associated with the virtual address from the memory;
receive a response for the memory request including data representing the copy of the page table entry associated with the virtual address; and
store the data representing the copy of the page table entry associated with the virtual address in a slot of the TLB.
17. The system of claim 15 , wherein the first memory management unit is included in a parallel processing unit.
18. The system of claim 17 , wherein the parallel processing unit is included in a system-on-chip (SoC) that includes a central processing unit and the second memory management unit coupled to a system bus.
19. The system of claim 15 , wherein the first page size is larger than the second page size and the first attribute is associated with the first page size and is not associated with the second page size.
20. The system of claim 15 , wherein the first attribute is not stored in the second page table and the second attribute is not stored in the first page table.