IP Library › Granted Patent US 12,581,973
Granted Patent B2
US 12,581,973 · App. 18/085,177 · Granted Mar 17, 2026

Semiconductor device

Inventor: Kei Murayama (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49844H01L23/3135H01L23/49816H01L23/49833H01L24/08H01L24/32H01L2224/08235H01L2224/32225H01L2924/13091H01L2924/182H01L2924/186
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Quick Facts
Patent No.
US 12,581,973
App. No.
18/085,177
Granted
Mar 17, 2026
Kind
B2
Abstract

A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, one or more through holes extending through the upper substrate in a thickness-wise direction, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin covering the upper surface of the upper substrate and filling the through holes.

Claims (24)

1 . A semiconductor device, comprising:

a lower substrate;

a semiconductor element mounted on an upper surface of the lower substrate;

an upper substrate disposed on an upper surface of the semiconductor element;

one or more through holes extending through the upper substrate in a thickness-wise direction;

an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element;

a wiring layer disposed on an upper surface of the upper substrate; and

a covering resin covering the upper surface of the upper substrate and filling the through holes, wherein

the upper substrate includes a substrate body and an adhesive layer, the adhesive layer being adhered to the upper surface of the semiconductor element and a lower surface of the upper substrate,

the through holes extend through the substrate body and the adhesive layer in the thickness-wise direction, and

the wiring layer has a thickness that is greater than that of the substrate body.

2 . The semiconductor device according to claim 1 , wherein the one or more through holes include one or more first through holes arranged in the vicinity of the semiconductor element in plan view, the first through holes extend through the wiring layer and the upper substrate in the thickness-wise direction, and the covering resin fills the first through holes.

3 . The semiconductor device according to claim 2 , wherein the semiconductor element is rectangular in plan view, and the first through holes are arranged adjacent to at least one side of the semiconductor element or at least one corner of the semiconductor element in plan view.

4 . The semiconductor device according to claim 3 , wherein the upper substrate is rectangular in plan view, the semiconductor element is disposed proximate to one of four corners of the upper substrate in plan view, and the first through holes are arranged in the vicinity of a corner of the semiconductor element that is located closest to the one of the four corners of the upper substrate in plan view.

5 . The semiconductor device according to claim 3 , wherein the first through holes are arranged in the vicinity of each of four corners of the semiconductor element in plan view.

6 . The semiconductor device according to claim 3 , wherein two of the first through holes are arranged for each of four sides of the semiconductor element in plan view.

7 . The semiconductor device according to claim 1 , wherein the one or more through holes include one or more second through holes arranged in the vicinity of the wiring layer without overlapping the wiring layer in plan view, the second through holes extend through the upper substrate in the thickness-wise direction, and the covering resin fills the second through holes.

8 . The semiconductor device according to claim 7 , wherein the second through holes are arranged adjacent to the wiring layer in plan view.

9 . The semiconductor device according to claim 1 , wherein the covering resin entirely covers the upper surface of the upper substrate exposed from the wiring layer and covers a side surface of the wiring layer.

10 . The semiconductor device according to claim 1 , wherein the covering resin covers an upper surface of the wiring layer, and the covering resin includes an opening that partially exposes the upper surface of the wiring layer.

11 . The semiconductor device according to claim 1 , wherein the encapsulation resin and the covering resin are formed continuously and integrally with each other.

12 . The semiconductor device according to claim 1 , wherein the encapsulation resin and the covering resin are formed from a same resin material.

13 . The semiconductor device according to claim 1 , wherein the encapsulation resin and the covering resin are formed from different resin materials.

14 . The semiconductor device according to claim 1 , wherein the upper substrate includes an opening extending through the substrate body and the adhesive layer to expose an electrode pad located on the upper surface of the semiconductor element, and the wiring layer fills the opening and is electrically connected to the electrode pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2022
From: MURAYAMA, KEI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 062161/0580 →
Priority Claims (1)
JP 2021-209839 · Dec 23, 2021 · national
Continuity (1)
Related Publication 20230207443A1 · Jun 29, 2023
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