IP Library Patent Application 18088541
Patent Application
App. No. 18/088,541

INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE HIGH

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Quick Facts
Patent No.
US None
App. No.
18/088,541
Abstract

Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

Claims (46)

1 . An integrated circuit structure, comprising:

a front side structure comprising:

a GaN-based device layer; and

one or more metallization layers above the GaN-based device layer;

a backside structure below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

2 . The integrated circuit structure of claim 1 , wherein the GaN-based device layer is on a silicon layer of the front side structure.

3 . The integrated circuit structure of claim 2 , wherein the backside structure is coupled to the GaN-based layer by one or more through-silicon vias.

4 . The integrated circuit structure of claim 1 , wherein the front side structure includes one or more metal insulator metal capacitors above the GaN-based device layer.

5 . An integrated circuit structure, comprising:

a front side structure comprising:

a GaN-based device layer;

one or more silicon-based transistors;

one or more metallization layers above the GaN-based device layer and the one or more silicon-based transistors;

a backside structure below and coupled to the GaN-based layer and the one or more silicon-based transistors, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

6 . The integrated circuit structure of claim 5 , wherein the one or more silicon-based transistors are one or more fin-based transistors.

7 . The integrated circuit structure of claim 5 , wherein the one or more silicon-based transistors are one or more nano-wire-based transistors.

8 . The integrated circuit structure of claim 5 , wherein the GaN-based device layer is on a silicon layer of the front side structure.

9 . The integrated circuit structure of claim 8 , wherein the backside structure is coupled to the GaN-based layer by one or more through-silicon vias.

10 . The integrated circuit structure of claim 5 , wherein the front side structure includes one or more metal insulator metal capacitors above the GaN-based device layer and the one or more silicon-based transistors.

11 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a front side structure comprising:

a GaN-based device layer; and

one or more metallization layers above the GaN-based device layer;

a backside structure below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

12 . The computing device of claim 11 , further comprising:

a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:

a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a front side structure comprising:

a GaN-based device layer;

one or more silicon-based transistors;

one or more metallization layers above the GaN-based device layer and the one or more silicon-based transistors;

a backside structure below and coupled to the GaN-based layer and the one or more silicon-based transistors, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

17 . The computing device of claim 16 , further comprising:

a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2023
From: THEN, HAN WUI; RADOSAVLJEVIC, MARKO; BADER, SAMUEL JAMES; ZUBAIR, AHMAD; KOIRALA, PRATIK; BEUMER, MICHAEL S.; VORA, HELI CHETANBHAI; BAN, IBRAHIM; NAIR, NITYAN; HOFF, THOMAS
To: INTEL CORPORATION
Reel/Frame 063550/0455 →