Sparsity compression for increased cache capacity
The disclosed computer-implemented method includes configuring a cache with a cache addressing scheme that increases a capacity of each entry of the cache, compressing a data segment for storing in the cache, and storing metadata of the compression in the cache with the compressed data segment. Various other methods, systems, and computer-readable media are also disclosed.
1 . A device comprising:
a cache; and
a controller configured to:
configure a cache with a cache addressing scheme that allows storing multiple compressed entries into an entry of the cache corresponding to an uncompressed entry size;
compress a data segment for storing in the cache; and
store, as one of the multiple compressed entries in the entry of the cache, the compressed data segment with metadata of the compression appended to an end of the compressed data segment, wherein the metadata represents index locations within the data segment at which zero values appeared in the data segment prior to compression.
2 . The device of claim 1 , wherein compressing the data segment further comprises shifting non-zero values together.
3 . The device of claim 1 , wherein the metadata comprises a bitmask of the index locations.
4 . The device of claim 1 , wherein the cache addressing scheme includes hashing one or more address bits of an address for the entry of the cache to map the entry to the multiple compressed entries.
5 . The device of claim 4 , wherein the address bits correspond to upper address bits.
6 . The device of claim 1 , wherein the cache addressing scheme includes reconfiguring a shadow tag indexing scheme for the cache.
7 . The device of claim 1 , wherein the controller is further configured to decompress, using the metadata, the compressed data segment for reading.
8 . The device of claim 7 , wherein decompressing the compressed data segment further comprises applying the metadata to shift non-zero values in the compressed data segment to locations corresponding to the data segment prior to compression.
9 . A system comprising:
a cache;
a compression circuit; and
a controller configured to:
configure the cache with a cache addressing scheme that allows storing multiple compressed entries into an entry of the cache correspond to an uncompressed entry size;
compress, using the compression circuit, a data segment for storing in the cache;
append metadata of the compression to an end of the compressed data segment, wherein the metadata represents index locations within the data segment at which zero values appeared in the data segment prior to compression; and
store the compressed data segment and the metadata as one of the multiple compressed entries in the cache entry based on the cache addressing scheme.
10 . The system of claim 9 , wherein the compression circuit comprises a zero detect circuit and a shift logic.
11 . The system of claim 10 , wherein compressing the data segment further comprises:
detecting, using the zero detect circuit, the index locations for zero values in the data segment;
saving, as a bitmask, the index locations as the metadata; and
shifting, using the shift logic, non-zero values together.
12 . The system of claim 9 , wherein the cache addressing scheme comprises:
hashing one or more upper address bits of an address for the entry of the cache to map the entry to the multiple compressed entries; and
reconfiguring a shadow tag indexing scheme for the cache in accordance with the cache addressing scheme.
13 . The system of claim 9 , wherein the controller is further configured to decompress, by applying the metadata to shift non-zero values in the compressed data segment to locations corresponding to the data segment prior to compression, the compressed data segment for reading.
14 . A method comprising:
configuring a cache with a cache addressing scheme that allows storing multiple compressed entries into an entry of the cache corresponding to an uncompressed entry size;
compressing, using a compression circuit, a data segment for storing in the cache;
storing, as one of the multiple compressed entries in the entry of the cache based on the cache addressing scheme, the compressed data segment with metadata of the compression appended to an end of the compressed data segment, wherein the metadata represents index locations within the data segment at which zero values appeared in the data segment prior to compression; and
decompressing, using a decompression circuit, the compressed data segment for reading the data segment.
15 . The method of claim 14 , wherein:
the compression circuit comprises a zero detect circuit and a first shift logic, and the decompression circuit comprises a second shift logic;
compressing the data segment further comprises shifting, using the first shift logic, nonzero values together; and
decompressing the compressed data segment further comprises applying the metadata to shift, using the second shift logic, non-zero values in the compressed data segment to locations corresponding to the data segment prior to compression.
16 . The method of claim 15 , wherein the metadata comprises a bitmask of the index locations detected by the zero detect circuit for zero values in the data segment.
17 . The method of claim 14 , wherein the cache addressing scheme comprises:
hashing one or more upper address bits of an address for the entry of the cache to map the entry to the multiple compressed entries; and
reconfiguring a shadow tag indexing scheme for the cache based on the cache addressing scheme.
18 . The device of claim 1 , wherein the controller is further configured to:
determine a compression ratio for compressing the data segment;
compare the determined compression ratio with a desired compression ratio that is based on a metadata unit size; and
forego compressing the data segment in response to the determined compression ratio not achieving the desired compression ratio.
19 . The device of claim 1 , wherein the controller is further configured to:
compress a second data segment for storing in the cache; and
store, as a second compressed entry of the multiple compressed entries in the entry of the cache, the compressed second data segment.