Method and apparatus for minimizing cache conflict misses
View Patent ↗A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.
1. A method for minimizing cache conflict misses, said method comprising:
providing a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field;
generating a hash value from a first group of bits within a virtual address;
storing said hash value in said hash value field of an entry within said translation table; and
in response to a match on said entry within said translation table during a cache access, retrieving said hash value of said matched entry from said translation table, and concatenating said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.
2. The method of claim 1 , wherein said first group of bits is a plurality of most significant bits (MSBs).
3. The method of claim 1 , wherein said second group of bits is a plurality of page bits within said virtual address.
4. The method of claim 3 , wherein said second group of bits is the five most significant page bits.
5. The method of claim 1 , wherein said hash value is represented by at least five bits.
6. The method of claim 1 , wherein said translation table facilitates the translation of a virtual address to a real address during a cache access.
7. A computer readable device having a computer program product for minimizing cache conflict misses, said computer readable device comprising:
computer program code for providing a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field, wherein said translation table facilitates the translation of a virtual address to a real address during a cache access;
computer program code for generating by a processor a hash value from a first group of bits within a virtual address;
computer program code for storing said hash value in said hash value field of an entry within said translation table; and
computer program code for, in response to a match on said entry within said translation table during a cache access, retrieving by said processor said hash value of said matched entry from said translation table, and concatenating by said processor said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.
8. The computer readable device of claim 7 , wherein said first group of bits is a plurality of most significant bits (MSBs).
9. The computer readable device of claim 7 , wherein said second group of bits is a plurality of page bits within said virtual address.
10. The computer readable device of claim 9 , wherein said second group of bits is the five most significant page bits.
11. The computer readable device of claim 7 , wherein said hash value is represented by at least five bits.
12. The computer readable device of claim 7 , wherein said translation table facilitates the translation of a virtual address to a real address during a cache access.
13. An apparatus for minimizing cache conflict misses, said apparatus comprising:
a hash function module for generating a hash value from a first group of bits within a virtual address;
a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field, wherein said translation table facilitates the translation of a virtual address to a real address during a cache access, wherein said hash value is stored in said hash value field of an entry within said translation table;
means for, in response to a match on said entry within said translation table during a cache access, retrieving said hash value of said matched entry from said translation table; and
a combine function module for concatenating said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.
14. The apparatus of claim 13 , wherein said first group of bits is a plurality of most significant bits (MSBs).
15. The apparatus of claim 13 , wherein said second group of bits is a plurality of page bits within said virtual address.
16. The apparatus of claim 15 , wherein said second group of bits is the five most significant page bits.
17. The apparatus of claim 13 , wherein said hash value is represented by at least five bits.
18. The apparatus of claim 13 , wherein said translation table facilitates the translation of a virtual address to a real address during a cache access.